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Searched refs:CRU_DPLL_CON0 (Results 1 – 2 of 2) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/shared/
A Dmisc_regs.h11 #define CRU_DPLL_CON0 0x40 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/src/
A Ddram.c46 mmio_write_32(CRU_BASE + CRU_DPLL_CON0, in ddr_set_pll()

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