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Searched refs:CRU_SOFTRSTS_CON (Results 1 – 9 of 9) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/secure/
A Dsecure.c147 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in secure_sgrf_init()
150 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in secure_sgrf_init()
156 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in secure_sgrf_init()
158 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in secure_sgrf_init()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/soc/
A Dsoc.c90 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), in sgrf_init()
93 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), in sgrf_init()
99 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); in sgrf_init()
101 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); in sgrf_init()
A Dsoc.h70 #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.c146 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_REQ); in sgrf_init()
148 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(3), DMA_SOFTRST_RLS); in sgrf_init()
A Dsoc.h44 #define CRU_SOFTRSTS_CON(n) (0x300 + ((n) * 4)) macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/pmu/
A Dpmu.c217 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), in cpus_power_domain_on()
226 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), BIT(cpu_id) << 16); in cpus_power_domain_on()
242 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(0), in cpus_power_domain_off()
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/soc/
A Dsoc.h68 #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/soc/
A Dsoc.h35 #define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/ddr/
A Dddr_rk3368.c436 p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10); in ddr_reg_save()

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