Searched refs:CTX_GPREGS_OFFSET (Results 1 – 13 of 13) sorted by relevance
| /tf-a-ffa_el3_spmc/lib/cpus/aarch64/ |
| A D | wa_cve_2017_5715_bpiall.S | 26 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
27 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
28 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
29 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
30 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
31 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
32 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
33 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
34 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
35 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
[all …]
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| A D | wa_cve_2017_5715_mmu.S | 20 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
60 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| A D | neoverse_n1.S | 650 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
651 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
652 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
653 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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| A D | denver.S | 33 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
54 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| A D | cortex_a76.S | 41 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
106 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| /tf-a-ffa_el3_spmc/bl31/aarch64/ |
| A D | ea_delegate.S | 53 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
66 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
67 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
68 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
112 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
113 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
114 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
118 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
135 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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| A D | runtime_exceptions.S | 64 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
100 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
139 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
154 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
179 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
182 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
196 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
551 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
556 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
557 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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| A D | crash_reporting.S | 222 add x7, sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0
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| /tf-a-ffa_el3_spmc/lib/el3_runtime/aarch64/ |
| A D | context.S | 681 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
682 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
683 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
684 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
685 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
808 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
809 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
810 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
811 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
812 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
[all …]
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| /tf-a-ffa_el3_spmc/include/arch/aarch64/ |
| A D | el3_common_macros.S | 470 stp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
472 ldp x29, x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29]
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| /tf-a-ffa_el3_spmc/include/lib/el3_runtime/aarch64/ |
| A D | context.h | 16 #define CTX_GPREGS_OFFSET U(0x0) macro
56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
448 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
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| /tf-a-ffa_el3_spmc/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 49 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
50 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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| /tf-a-ffa_el3_spmc/bl1/aarch64/ |
| A D | bl1_exceptions.S | 85 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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