| /tf-a-ffa_el3_spmc/services/spd/tlkd/ |
| A D | tlkd_pm.c | 55 write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_SUSPEND); in cpu_suspend_handler()
88 write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_RESUME); in cpu_resume_handler()
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| /tf-a-ffa_el3_spmc/services/std_svc/spmd/ |
| A D | spmd_pm.c | 26 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); in spmd_build_spmc_message()
140 CTX_GPREG_X0); in spmd_cpu_off_handler()
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| /tf-a-ffa_el3_spmc/lib/cpus/aarch64/ |
| A D | wa_cve_2017_5715_mmu.S | 20 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
60 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| A D | denver.S | 33 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
54 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| A D | wa_cve_2017_5715_bpiall.S | 26 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
291 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| A D | neoverse_n1.S | 650 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| /tf-a-ffa_el3_spmc/services/std_svc/spm/spmc/ |
| A D | spmc_pm.c | 28 write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32); in spmc_build_pm_message()
149 resp = read_ctx_reg(get_gpregs_ctx(&ec->cpu_ctx), CTX_GPREG_X0); in spmc_cpu_off_handler()
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| A D | spmc_setup.c | 184 CTX_GPREG_X0, in spmc_el1_sp_setup()
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| /tf-a-ffa_el3_spmc/services/spd/opteed/ |
| A D | opteed_pm.c | 71 write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), CTX_GPREG_X0, in opteed_cpu_suspend_handler()
142 CTX_GPREG_X0, in opteed_cpu_suspend_finish_handler()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/ |
| A D | tegra_fiq_glue.c | 139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
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| /tf-a-ffa_el3_spmc/bl31/aarch64/ |
| A D | ea_delegate.S | 66 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
112 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| A D | runtime_exceptions.S | 551 str x0, [x6, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| A D | crash_reporting.S | 222 add x7, sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
| A D | plat_sip_calls.c | 117 CTX_GPREG_X0, (uint64_t)(mce_ret)); in plat_sip_handler()
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| /tf-a-ffa_el3_spmc/include/arch/aarch64/ |
| A D | smccc_helpers.h | 23 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \
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| /tf-a-ffa_el3_spmc/services/spd/tspd/ |
| A D | tspd_pm.c | 161 CTX_GPREG_X0, in tspd_cpu_suspend_finish_handler()
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| /tf-a-ffa_el3_spmc/services/std_svc/spm/common/ |
| A D | logical_mm_sp.c | 69 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X0, smc_fid); in spmc_sp_call()
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| /tf-a-ffa_el3_spmc/include/lib/el3_runtime/aarch64/ |
| A D | context.h | 17 #define CTX_GPREG_X0 U(0x0) macro
474 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
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| /tf-a-ffa_el3_spmc/plat/qti/qtiseclib/src/ |
| A D | qtiseclib_cb_interface.c | 146 qti_ns_ctx->x0 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0); in qtiseclib_cb_get_ns_ctx()
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| /tf-a-ffa_el3_spmc/services/std_svc/spm/spm_mm/ |
| A D | spm_mm_main.c | 237 write_ctx_reg(get_gpregs_ctx(cpu_ctx), CTX_GPREG_X0, smc_fid); in spm_mm_sp_call()
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| /tf-a-ffa_el3_spmc/bl31/ |
| A D | ehf.c | 352 write_ctx_reg(get_gpregs_ctx(ns_ctx), CTX_GPREG_X0, preempt_ret_code); in ehf_allow_ns_preemption()
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| /tf-a-ffa_el3_spmc/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 49 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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| /tf-a-ffa_el3_spmc/services/std_svc/sdei/ |
| A D | sdei_intr_mgmt.c | 326 SMC_SET_GP(ctx, CTX_GPREG_X0, (uint64_t) map->ev_num); in setup_ns_dispatch()
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| /tf-a-ffa_el3_spmc/lib/el3_runtime/aarch64/ |
| A D | context.S | 681 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
808 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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