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Searched refs:DDR_STDBY_BASE (Results 1 – 2 of 2) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/px30/
A Dpx30_def.h118 #define DDR_STDBY_BASE 0xff620000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/pmu/
A Dpmu.c655 ddr_data.ddrstdby_con0 = mmio_read_32(DDR_STDBY_BASE + 0x0); in ddr_sleep_config()
656 mmio_write_32(DDR_STDBY_BASE + 0x0, BITS_WITH_WMASK(0x0, 0x1, 0)); in ddr_sleep_config()
687 mmio_write_32(DDR_STDBY_BASE + 0x0, in ddr_sleep_config_restore()

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