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Searched refs:DDR_UPCTL_BASE (Results 1 – 5 of 5) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/
A Drk3328_def.h73 #define DDR_UPCTL_BASE 0xff780000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/px30/
A Dpx30_def.h112 #define DDR_UPCTL_BASE 0xff600000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/pmu/
A Dpmu.c493 sram_data.pd_sr_idle_save = mmio_read_32(DDR_UPCTL_BASE + in ddr_suspend()
497 mmio_clrbits_32(DDR_UPCTL_BASE + DDR_PCTL2_PWRCTL, SELFREF_EN); in ddr_suspend()
553 mmio_setbits_32(DDR_UPCTL_BASE + DDR_PCTL2_PWRCTL, in dmc_restore()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.c58 MAP_REGION_FLAT(DDR_UPCTL_BASE, DDR_UPCTL_SIZE,
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/pmu/
A Dpmu.c647 ddr_data.ddrc_pwrctrl = mmio_read_32(DDR_UPCTL_BASE + 0x30); in ddr_sleep_config()
648 mmio_write_32(DDR_UPCTL_BASE + 0x30, BITS_WITH_WMASK(0x0, 0x3, 0)); in ddr_sleep_config()
657 while ((mmio_read_32(DDR_UPCTL_BASE + 0x4) & 0x7) != 1) in ddr_sleep_config()
695 mmio_write_32(DDR_UPCTL_BASE + 0x30, in ddr_sleep_config_restore()

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