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Searched refs:DFD_INTERNAL_CTL (Results 1 – 4 of 4) sorted by relevance

/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/dfd/
A Dplat_dfd.c22 sync_writel(DFD_INTERNAL_CTL, 0x5); in dfd_setup()
25 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13); in dfd_setup()
35 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3); in dfd_setup()
38 mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19); in dfd_setup()
99 mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4); in dfd_setup()
A Dplat_dfd.h24 #define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00) macro
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/
A Dplat_debug.c36 sync_writel(DFD_INTERNAL_CTL, 0x1); in circular_buffer_unlock()
42 sync_writel(DFD_INTERNAL_CTL, 0x0); in circular_buffer_lock()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/include/
A Dplat_debug.h16 #define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00) macro

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