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Searched refs:DVFS_DFLL_CTRL (Results 1 – 2 of 2) sorted by relevance

/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A Dplat_psci_handlers.c139 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); in tegra_soc_get_target_pwr_state()
230 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, in tegra_soc_pwr_domain_suspend()
528 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, in tegra_soc_pwr_domain_on_finish()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t210/
A Dtegra_def.h259 #define DVFS_DFLL_CTRL U(0x00) macro

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