| /tf-a-ffa_el3_spmc/plat/amlogic/gxbb/ |
| A D | gxbb_bl31_setup.c | 108 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
| /tf-a-ffa_el3_spmc/plat/renesas/common/aarch64/ |
| A D | platform_common.c | 224 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
227 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
229 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
231 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
233 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
235 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
243 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
[all …]
|
| /tf-a-ffa_el3_spmc/plat/amlogic/g12a/ |
| A D | g12a_bl31_setup.c | 108 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
|
| /tf-a-ffa_el3_spmc/plat/amlogic/gxl/ |
| A D | gxl_bl31_setup.c | 124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
126 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
128 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
130 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
132 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
134 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
136 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
138 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
140 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
| /tf-a-ffa_el3_spmc/plat/amlogic/axg/ |
| A D | axg_bl31_setup.c | 134 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
136 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
138 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
140 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
142 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
144 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
146 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
148 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
150 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
|
| /tf-a-ffa_el3_spmc/plat/qemu/common/ |
| A D | qemu_gicv2.c | 12 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
13 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/hisilicon/poplar/ |
| A D | poplar_gicv2.c | 17 POPLAR_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
18 POPLAR_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/arm/common/ |
| A D | arm_gicv2.c | 28 PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
29 PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/st/stm32mp1/ |
| A D | stm32mp1_gic.c | 28 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
29 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/rockchip/rk3288/ |
| A D | rk3288_def.h | 123 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
125 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
|
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/ |
| A D | plat_setup.c | 192 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
194 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
196 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
|
| /tf-a-ffa_el3_spmc/plat/marvell/armada/common/ |
| A D | marvell_gicv2.c | 46 PLAT_MARVELL_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
47 PLAT_MARVELL_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/rockchip/rk3328/ |
| A D | rk3328_def.h | 143 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
145 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
|
| /tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
| A D | plat_mt_gic.c | 15 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey/ |
| A D | hikey_bl31_setup.c | 38 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
| /tf-a-ffa_el3_spmc/plat/rockchip/px30/ |
| A D | px30_def.h | 165 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
167 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
|
| /tf-a-ffa_el3_spmc/plat/qemu/common/sp_min/ |
| A D | sp_min_setup.c | 55 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
56 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/layerscape/common/tsp/ |
| A D | ls_tsp_setup.c | 18 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/ |
| A D | hikey960_bl31_setup.c | 40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
42 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
| A D | hikey960_bl1_setup.c | 52 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
54 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
|
| /tf-a-ffa_el3_spmc/plat/intel/soc/agilex/ |
| A D | bl31_plat_setup.c | 84 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
85 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/intel/soc/stratix10/ |
| A D | bl31_plat_setup.c | 92 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
93 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
|
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
| A D | plat_setup.c | 237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
|
| /tf-a-ffa_el3_spmc/plat/rockchip/rk3368/ |
| A D | rk3368_def.h | 114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
|
| /tf-a-ffa_el3_spmc/drivers/arm/gic/v2/ |
| A D | gicv2_helpers.c | 139 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); in gicv2_secure_spis_configure_props()
192 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); in gicv2_secure_ppi_sgi_setup_props()
|