| /tf-a-ffa_el3_spmc/ |
| A D | dco.txt | 15 By making a contribution to this project, I certify that:
17 (a) The contribution was created in whole or in part by me and I
23 license and I have the right under that license to submit that
25 by me, under the same open source license (unless I am
30 person who certified (a), (b) or (c) and I have not modified
33 (d) I understand and agree that this project and the contribution
35 personal information I submit with it, including my sign-off) is
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| /tf-a-ffa_el3_spmc/plat/xilinx/common/ |
| A D | ipi.c | 36 #define IPI_REG_BASE(I) (ipi_table[(I)].ipi_reg_base) argument
39 #define IPI_BIT_MASK(I) (ipi_table[(I)].ipi_bit_mask) argument
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| /tf-a-ffa_el3_spmc/plat/xilinx/common/include/ |
| A D | ipi.h | 31 #define IPI_IS_SECURE(I) ((ipi_table[(I)].secure_only & \ argument
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| /tf-a-ffa_el3_spmc/docs/resources/diagrams/plantuml/ |
| A D | fip-secure-partitions.puml | 109 <i>signature</I>
121 <i>signature</I>
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| /tf-a-ffa_el3_spmc/docs/plat/ |
| A D | intel-agilex.rst | 57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
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| A D | intel-stratix10.rst | 57 aarch64-linux-gnu-objcopy -I binary -O ihex --change-addresses 0xffe00000 bl2.bin bl2.hex
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| A D | ls1043a.rst | 7 in a flexible I/O package supporting fanless designs. This SoC is a
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| A D | rz-g2.rst | 47 ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB
48 ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K
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| A D | rcar-gen3.rst | 43 ARM CA57 (ARMv8) 1.5 GHz quad core, with NEON/VFPv4, L1$ I/D
45 ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K,
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| A D | rpi3.rst | 127 | I/O |
139 different mappings than the Arm cores in which the I/O addresses don't overlap
265 | I/O |
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| /tf-a-ffa_el3_spmc/fdts/ |
| A D | stm32mp15-pinctrl.dtsi | 91 pinmux = <STM32_PINMUX('I', 8, ANALOG)>; /* RTC_OUT2_RMP */
267 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
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| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | faq.rst | 4 How do I update my changes?
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| A D | code-review-guidelines.rst | 85 - Bugs ("I think you need a logical \|\| rather than a bitwise \|.")
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| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | sdei.rst | 253 - SDEI events must be unmasked on the PE. I.e. the client must have called
265 - A dispatch for the same event must not be outstanding. I.e. it hasn't already
284 I.e. the caller must make sure that the requested dispatch has sufficient
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| A D | secure-partition-manager.rst | 814 Direct Memory Access (DMA) requests from system I/O devices.
820 - Protection: An I/O device can be prohibited from read, write access to a
827 several I/O devices along with Interconnect and Memory system.
842 - Traffic (memory transactions) from each upstream I/O peripheral device,
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| A D | ras.rst | 235 documentation. I.e., for interrupts, the priority management is implicit; but
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| A D | exception-handling.rst | 467 - *Fast* SMCs are atomic from the caller's point of view. I.e., they return
474 Yielding SMC. I.e., the caller might observe a Yielding SMC returning when
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| A D | secure-partition-manager-mm.rst | 446 - ``I=1``
459 - ``D,A,I,F=1``
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | interrupt-framework-design.rst | 214 #. Interrupt exceptions (``PSTATE.I`` and ``F`` bits) are masked during execution
557 #. **CSS=0, TEL3=0**. If ``PSTATE.I=0``, non-secure interrupts will be
567 If ``PSTATE.I=1`` then the non-secure interrupt will pend until execution
571 be visible to the SP. The ``PSTATE.I`` bit in Secure-EL1/Secure-EL0 will
626 ``PSTATE.I`` and ``PSTATE.F`` bits set.
852 exceptions are unmasked i.e. ``PSTATE.I=0``, and a non-secure interrupt will
899 it is generated during execution in the TSP with ``PSTATE.I`` = 0 when the
924 vector table when ``PSTATE.I`` and ``PSTATE.F`` bits are 0. As described earlier,
990 assuming ``P.STATE.I=0`` in the non secure state :
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| A D | firmware-design.rst | 241 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
271 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
464 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
2665 I.e:
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| /tf-a-ffa_el3_spmc/make_helpers/ |
| A D | build_macros.mk | 25 uppercase_table:=a,A b,B c,C d,D e,E f,F g,G h,H i,I j,J k,K l,L m,M n,N o,O p,P q,Q r,R s,S t,T u,…
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| /tf-a-ffa_el3_spmc/docs/getting_started/ |
| A D | porting-guide.rst | 55 I/O addresses to reduce their virtual address space. All other addresses
908 FWU metadata, and update I/O policies of active/updated images using retrieved
910 Further I/O layer operations such as I/O open, I/O read, etc. on these
913 In Arm platforms, this function is used to set an I/O policy of the FIP image,
926 responsible for setting up the platform I/O policy of the requested metadata
932 statically in I/O policy.
937 the I/O policy of the FWU metadata image.
938 Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
942 Alongside, returns device handle and image specification from the I/O policy
2902 received at EL3 while one is already being handled. I.e., a call to
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| /tf-a-ffa_el3_spmc/docs/plat/arm/fvp/ |
| A D | index.rst | 283 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
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| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 1607 - socionext: uniphier: Make on-chip SRAM and I/O register regions configurable
2526 - ccn: Incorrect Region ID calculation for RN-I nodes
4403 - Added I/O abstraction framework, primarily to allow generic code to load
4405 been reworked to use the new framework. Semi-hosting and NOR flash I/O
4410 single binary image. The new FIP driver is another type of I/O driver. The
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