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Searched refs:MISCREG_PFCFG (Results 1 – 4 of 4) sorted by relevance

/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t186/
A Dtegra_def.h92 #define MISCREG_PFCFG U(0x200C) macro
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t194/
A Dtegra_def.h71 #define MISCREG_PFCFG U(0x200C) macro
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/
A Dplat_psci_handlers.c138 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); in tegra_soc_pwr_domain_suspend()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/
A Dplat_psci_handlers.c138 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); in tegra_soc_pwr_domain_suspend()

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