Home
last modified time | relevance | path

Searched refs:MPIDR (Results 1 – 21 of 21) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/common/aarch32/
A Dplat_helpers.S38 ldcopr r0, MPIDR
65 ldcopr r0, MPIDR
97 ldcopr r0, MPIDR
A Dpmu_sram_cpus_on.S23 ldcopr r0, MPIDR
/tf-a-ffa_el3_spmc/plat/arm/board/a5ds/aarch32/
A Da5ds_helpers.S70 ldcopr r0, MPIDR
84 ldcopr r0, MPIDR
/tf-a-ffa_el3_spmc/plat/arm/board/fvp/aarch32/
A Dfvp_helpers.S53 ldcopr r2, MPIDR
97 ldcopr r0, MPIDR
/tf-a-ffa_el3_spmc/plat/qemu/common/aarch32/
A Dplat_helpers.S25 ldcopr r0, MPIDR
48 ldcopr r0, MPIDR
/tf-a-ffa_el3_spmc/docs/design/
A Dpsci-pd-tree.rst17 tree. It also uses an MPIDR to find a node in the tree. The assumption that
19 code is not scalable. The use of an MPIDR also restricts the number of
38 using an MPIDR. There is no requirement to perform state coordination while
130 corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed
132 platform API have changed since it is required to validate the passed MPIDR. It
137 the index since there is no need to validate the MPIDR of the calling core.
147 Dealing with holes in MPIDR allocation
151 core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to
163 #. Implement more complex logic to convert a valid MPIDR to a core index while
173 allow use of a simpler logic to convert an MPIDR to a core index.
[all …]
A Dfirmware-design.rst2513 These macros accept the CPU's MPIDR value, or its ordinal position
/tf-a-ffa_el3_spmc/plat/arm/common/aarch32/
A Darm_helpers.S22 ldcopr r0, MPIDR
/tf-a-ffa_el3_spmc/plat/arm/board/corstone700/common/
A Dcorstone700_helpers.S61 ldcopr r0, MPIDR
/tf-a-ffa_el3_spmc/docs/
A Dglobal_substitutions.txt26 .. |MPIDR| replace:: :term:`MPIDR`
A Dglossary.rst91 MPIDR
A Dchange-log.rst487 - Added helper to calculate the position shift from MPIDR
1142 - Fixed initialization issues caused by incorrect MPIDR topology mapping
3405 accessing MPIDR assume that the `MT` bit is set for the platform and
/tf-a-ffa_el3_spmc/plat/st/stm32mp1/
A Dstm32mp1_helper.S113 ldcopr r0, MPIDR
140 ldcopr r0, MPIDR
/tf-a-ffa_el3_spmc/docs/plat/arm/
A Darm-build-options.rst38 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag
39 is set, the functions which deal with MPIDR assume that the ``MT`` bit in
40 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
/tf-a-ffa_el3_spmc/docs/components/
A Dplatform-interrupt-controller-API.rst207 the ID of the SGI. The second parameter, ``target``, must be the MPIDR of the
233 - ``INTR_ROUTING_MODE_PE`` means the interrupt is routed to the PE whose MPIDR
A Dsecure-partition-manager.rst406 - *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
/tf-a-ffa_el3_spmc/docs/plat/arm/arm_fpga/
A Dindex.rst30 - ``SUPPORT_UNKNOWN_MPID`` : Boolean option to allow unknown MPIDR registers.
/tf-a-ffa_el3_spmc/include/arch/aarch32/
A Darch_helpers.h217 DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) in DEFINE_SYSREG_RW_FUNCS()
A Darch.h503 #define MPIDR p15, 0, c0, c0, 5 macro
/tf-a-ffa_el3_spmc/docs/getting_started/
A Dporting-guide.rst833 This function validates the ``MPIDR`` of a CPU and converts it to an index,
835 case the ``MPIDR`` is invalid, this function returns -1. This function will only
2055 ``plat_sdei_handle_masked_trigger``. The MPIDR of the PE that received the
2129 CPU is specified by its ``MPIDR`` in a PSCI ``CPU_ON`` call. The ``pwr_domain_on()``
2286 by the ``MPIDR`` (first argument). The generic code expects the platform to
2485 domain. The target power domain is identified by using both ``MPIDR`` (first
2504 the power state of a node (identified by the first parameter, the ``MPIDR``) in
/tf-a-ffa_el3_spmc/docs/plat/arm/fvp/
A Dindex.rst140 like shifted affinity format for MPIDR, cannot be detected at build time

Completed in 49 milliseconds