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Searched refs:MPIDR_AFF2_SHIFT (Results 1 – 18 of 18) sorted by relevance

/tf-a-ffa_el3_spmc/plat/arm/common/
A Darm_topology.c27 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | in arm_check_mpidr()
29 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
/tf-a-ffa_el3_spmc/plat/marvell/armada/common/
A Dmarvell_topology.c51 MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) in marvell_check_mpidr()
/tf-a-ffa_el3_spmc/plat/arm/board/morello/aarch64/
A Dmorello_helper.S44 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/arm/board/tc/include/
A Dtc_helpers.S42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/arm/board/n1sdp/aarch64/
A Dn1sdp_helper.S43 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/arm/board/corstone700/common/
A Dcorstone700_helpers.S91 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/drivers/arm/css/scpi/
A Dcss_scpi.c143 state |= ((mpidr >> MPIDR_AFF2_SHIFT) & 0x0f) << 4; /* Cluster ID */ in scpi_set_css_power_state()
200 cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
/tf-a-ffa_el3_spmc/plat/arm/css/sgm/aarch64/
A Dcss_sgm_helpers.S44 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/arm/css/sgi/aarch64/
A Dsgi_helper.S46 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/arm/board/a5ds/aarch32/
A Da5ds_helpers.S117 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/arm/board/fvp/aarch32/
A Dfvp_helpers.S134 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/arm/board/fvp/aarch64/
A Dfvp_helpers.S169 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/plat/qti/common/src/
A Dqti_common.c65 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in plat_qti_my_cluster_pos()
/tf-a-ffa_el3_spmc/plat/brcm/common/
A Dbrcm_scpi.c138 state |= ((mpidr >> MPIDR_AFF2_SHIFT) & 0x0f) << 4; /* Cluster ID */ in scpi_set_brcm_power_state()
/tf-a-ffa_el3_spmc/plat/arm/board/arm_fpga/aarch64/
A Dfpga_helpers.S142 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
/tf-a-ffa_el3_spmc/common/
A Dfdt_fixup.c374 mpidr = ((i - 1) << MPIDR_AFF2_SHIFT) | in fdt_add_cpus_node()
/tf-a-ffa_el3_spmc/include/arch/aarch32/
A Darch.h35 #define MPIDR_AFF2_SHIFT U(16) macro
48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
/tf-a-ffa_el3_spmc/include/arch/aarch64/
A Darch.h37 #define MPIDR_AFF2_SHIFT U(16) macro
52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \

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