| /tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
| A D | power_tracer.c | 19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
|
| A D | plat_pm.c | 66 clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in get_cluster_data()
|
| /tf-a-ffa_el3_spmc/plat/mediatek/mt8173/ |
| A D | power_tracer.c | 19 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
24 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
29 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, in trace_power_flow()
34 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
38 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
42 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); in trace_power_flow()
|
| A D | plat_pm.c | 109 clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in get_cluster_data()
|
| /tf-a-ffa_el3_spmc/plat/arm/board/morello/aarch64/ |
| A D | morello_helper.S | 42 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
45 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/board/tc/include/ |
| A D | tc_helpers.S | 36 lsl x3, x0, #MPIDR_AFFINITY_BITS
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/board/n1sdp/aarch64/ |
| A D | n1sdp_helper.S | 41 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/css/sgm/aarch64/ |
| A D | css_sgm_helpers.S | 38 lsr x3, x0, #MPIDR_AFFINITY_BITS
42 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/css/sgi/aarch64/ |
| A D | sgi_helper.S | 44 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
45 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
46 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
47 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/board/a5ds/aarch32/ |
| A D | a5ds_helpers.S | 112 lsleq r3, r0, #MPIDR_AFFINITY_BITS
115 ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
116 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
117 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/aarch32/ |
| A D | fvp_helpers.S | 129 lsleq r3, r0, #MPIDR_AFFINITY_BITS
132 ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
133 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
134 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/board/corstone700/common/ |
| A D | corstone700_helpers.S | 89 ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
90 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
91 ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/aarch64/ |
| A D | fvp_helpers.S | 163 lsl x3, x0, #MPIDR_AFFINITY_BITS
167 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
168 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
169 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/board/arm_fpga/aarch64/ |
| A D | fpga_helpers.S | 136 lsl x3, x0, #MPIDR_AFFINITY_BITS
140 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
141 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
142 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/ |
| A D | hikey960_pm.c | 66 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_on()
97 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_off()
193 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_suspend()
269 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey960_pwr_domain_suspend_finish()
|
| /tf-a-ffa_el3_spmc/plat/socionext/uniphier/ |
| A D | uniphier_helpers.S | 21 lsr x0, x0, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/mediatek/mt8183/ |
| A D | plat_dcm.c | 78 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in plat_dcm_restore_cluster_on()
|
| /tf-a-ffa_el3_spmc/plat/qti/common/src/aarch64/ |
| A D | qti_helpers.S | 40 lsr x0, x0, #MPIDR_AFFINITY_BITS
|
| /tf-a-ffa_el3_spmc/plat/arm/css/common/aarch32/ |
| A D | css_helpers.S | 60 eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
|
| /tf-a-ffa_el3_spmc/plat/arm/css/common/aarch64/ |
| A D | css_helpers.S | 80 eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
|
| /tf-a-ffa_el3_spmc/plat/mediatek/mt8173/drivers/spm/ |
| A D | spm_mcdi.c | 307 int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in spm_mcdi_wfi_sel_enter()
358 int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in spm_mcdi_wfi_sel_leave()
|
| /tf-a-ffa_el3_spmc/plat/qemu/common/aarch64/ |
| A D | plat_helpers.S | 35 add x0, x1, x0, LSR #(MPIDR_AFFINITY_BITS -\
|
| /tf-a-ffa_el3_spmc/plat/hisilicon/hikey/ |
| A D | hikey_pm.c | 102 (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; in hikey_pwr_domain_suspend()
|
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/ |
| A D | plat_psci_handlers.c | 325 MPIDR_AFFINITY_BITS; in tegra_soc_pwr_domain_on()
|
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
| A D | plat_psci_handlers.c | 353 MPIDR_AFFINITY_BITS; in tegra_soc_pwr_domain_on()
|