MPIDR_AFFLVL2 (reference) in projects: tf-a-ffa_el3_spmc

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Searched refs:MPIDR_AFFLVL2 (Results 1 – 25 of 40) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/include/
A D	platform_def.h	`38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/include/
A D	platform_def.h	`38 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 50 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/
A D	platform_def.h	`40 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 52 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/rockchip/px30/include/
A D	platform_def.h	`41 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 53 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/include/
A D	platform_def.h	`39 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 53 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/
A D	plat_topology.c	`27 return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; in plat_get_aff_state()`
A D	plat_pm.c	`190 assert(afflvl <= MPIDR_AFFLVL2); in plat_do_plat_actions() 348 if (afflvl >= MPIDR_AFFLVL2) { in plat_affinst_suspend() 397 if (afflvl >= MPIDR_AFFLVL2) { in plat_affinst_suspend_finish()`
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/include/
A D	platform_def.h	`35 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)`
/tf-a-ffa_el3_spmc/plat/amlogic/axg/include/
A D	platform_def.h	`27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/layerscape/board/ls1043/include/
A D	ls_def.h	`32 #define LS_PWR_LVL2 MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/imx/imx8qm/include/
A D	platform_def.h	`28 #define IMX_PWR_LVL2 MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/nxp/soc-lx2160a/include/
A D	soc.h	`103 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/qti/sc7180/inc/
A D	platform_def.h	`33 #define QTI_PWR_LVL2 MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/include/
A D	platform_def.h	`32 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/arm/board/arm_fpga/include/
A D	platform_def.h	`82 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/
A D	platform_def.h	`46 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/include/plat/marvell/armada/a3k/common/
A D	marvell_def.h	`37 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/include/
A D	platform_def.h	`39 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/include/plat/marvell/armada/a8k/common/
A D	marvell_def.h	`34 #define MARVELL_PWR_LVL2 MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/ti/k3/include/
A D	platform_def.h	`40 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A D	plat_psci_handlers.c	`114 if (lvl == MPIDR_AFFLVL2) in tegra_soc_get_target_pwr_state() 175 } else if (((lvl == MPIDR_AFFLVL2) \|\| (lvl == MPIDR_AFFLVL1)) && in tegra_soc_get_target_pwr_state() 199 unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; in tegra_soc_pwr_domain_suspend()`
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mq/include/
A D	platform_def.h	`22 #define IMX_PWR_LVL2 MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/amlogic/axg/
A D	axg_pm.c	`124 if (target_state->pwr_domain_state[MPIDR_AFFLVL2] == in axg_pwr_domain_off()`
/tf-a-ffa_el3_spmc/plat/socionext/synquacer/include/
A D	platform_def.h	`22 #define SQ_PWR_LVL2 MPIDR_AFFLVL2`
/tf-a-ffa_el3_spmc/plat/renesas/common/include/
A D	platform_def.h	`90 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2`

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