/tf-a-ffa_el3_spmc/services/spd/tspd/ |
A D | tspd_main.c | 80 cm_el1_sysregs_context_restore(NON_SECURE); in tspd_handle_sp_preemption() 81 cm_set_next_eret_context(NON_SECURE); in tspd_handle_sp_preemption() 157 cm_el1_sysregs_context_save(NON_SECURE); in tspd_sel1_interrupt_handler() 177 cm_el1_sysregs_context_save(NON_SECURE); in tspd_sel1_interrupt_handler() 417 cm_set_next_eret_context(NON_SECURE); in tspd_smc_handler() 502 assert(NON_SECURE == in tspd_smc_handler() 506 cm_prepare_el3_exit(NON_SECURE); in tspd_smc_handler() 507 SMC_RET0(cm_get_context(NON_SECURE)); in tspd_smc_handler() 658 cm_set_next_eret_context(NON_SECURE); in tspd_smc_handler() 699 cm_set_next_eret_context(NON_SECURE); in tspd_smc_handler() [all …]
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/tf-a-ffa_el3_spmc/bl32/sp_min/ |
A D | sp_min_main.c | 49 assert(security_state == NON_SECURE); 55 assert(security_state == NON_SECURE); in smc_set_next_ctx() 71 assert(security_state == NON_SECURE); in cm_get_context() 81 assert(security_state == NON_SECURE); in cm_set_context() 94 assert(security_state == NON_SECURE); in cm_get_context_by_index() 105 assert(security_state == NON_SECURE); in cm_set_context_by_index() 128 cpu_context_t *ctx = cm_get_context(NON_SECURE); in sp_min_prepare_next_image_entry() 139 smc_set_next_ctx(NON_SECURE); in sp_min_prepare_next_image_entry() 142 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), in sp_min_prepare_next_image_entry() 211 cpu_context_t *ctx = cm_get_context(NON_SECURE); in sp_min_warm_boot() [all …]
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/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
A D | plat_memctrl.c | 38 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE), 39 mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, DISABLE), 40 mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, DISABLE), 50 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE), 58 mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE), 60 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE), 64 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE), 65 mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE), 66 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE), 70 mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE), [all …]
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/tf-a-ffa_el3_spmc/services/spd/tlkd/ |
A D | tlkd_main.c | 76 assert(handle == cm_get_context(NON_SECURE)); in tlkd_interrupt_handler() 79 cm_el1_sysregs_context_save(NON_SECURE); in tlkd_interrupt_handler() 141 set_interrupt_rm_flag(flags, NON_SECURE); in tlkd_setup() 237 ns_cpu_context = cm_get_context(NON_SECURE); in tlkd_smc_handler() 245 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_smc_handler() 246 cm_set_next_eret_context(NON_SECURE); in tlkd_smc_handler() 303 cm_el1_sysregs_context_save(NON_SECURE); in tlkd_smc_handler() 397 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_smc_handler() 398 cm_set_next_eret_context(NON_SECURE); in tlkd_smc_handler() 472 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_smc_handler() [all …]
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A D | tlkd_common.c | 31 cm_el1_sysregs_context_restore(NON_SECURE); in tlkd_va_translate() 34 write_scr(cm_get_scr_el3(NON_SECURE)); in tlkd_va_translate()
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/tf-a-ffa_el3_spmc/services/spd/opteed/ |
A D | opteed_main.c | 65 assert(handle == cm_get_context(NON_SECURE)); in opteed_sel1_interrupt_handler() 68 cm_el1_sysregs_context_save(NON_SECURE); in opteed_sel1_interrupt_handler() 216 assert(handle == cm_get_context(NON_SECURE)); in opteed_smc_handler() 218 cm_el1_sysregs_context_save(NON_SECURE); in opteed_smc_handler() 301 set_interrupt_rm_flag(flags, NON_SECURE); in opteed_smc_handler() 367 ns_cpu_context = cm_get_context(NON_SECURE); in opteed_smc_handler() 371 cm_el1_sysregs_context_restore(NON_SECURE); in opteed_smc_handler() 372 cm_set_next_eret_context(NON_SECURE); in opteed_smc_handler() 382 ns_cpu_context = cm_get_context(NON_SECURE); in opteed_smc_handler() 390 cm_el1_sysregs_context_restore(NON_SECURE); in opteed_smc_handler() [all …]
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/tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/ |
A D | tegra_fiq_glue.c | 42 cpu_context_t *ctx = cm_get_context(NON_SECURE); in tegra_fiq_interrupt_handler() 60 cm_el1_sysregs_context_save(NON_SECURE); in tegra_fiq_interrupt_handler() 73 cm_set_elr_el3(NON_SECURE, ns_fiq_handler_addr); in tegra_fiq_interrupt_handler() 129 cpu_context_t *ctx = cm_get_context(NON_SECURE); in tegra_fiq_get_intr_context()
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/tf-a-ffa_el3_spmc/services/spd/trusty/ |
A D | trusty.c | 100 ctx_smc = cm_get_context(NON_SECURE); in trusty_context_switch() 147 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_ENTER, 0, 0, 0); in trusty_fiq_handler() 205 ret = trusty_context_switch(NON_SECURE, SMC_FC_FIQ_EXIT, 0, 0, 0); in trusty_fiq_exit() 297 ret = trusty_context_switch(NON_SECURE, smc_fid, x1, in trusty_smc_handler() 321 fpregs_context_save(get_fpregs_ctx(cm_get_context(NON_SECURE))); in trusty_init() 322 cm_el1_sysregs_context_save(NON_SECURE); in trusty_init() 346 cm_el1_sysregs_context_restore(NON_SECURE); in trusty_init() 347 fpregs_context_restore(get_fpregs_ctx(cm_get_context(NON_SECURE))); in trusty_init() 348 cm_set_next_eret_context(NON_SECURE); in trusty_init() 483 set_interrupt_rm_flag(flags, NON_SECURE); in trusty_setup() [all …]
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/tf-a-ffa_el3_spmc/bl31/ |
A D | bl31_context_mgmt.c | 22 assert(security_state <= NON_SECURE); in cm_get_context() 33 assert(security_state <= NON_SECURE); in cm_set_context()
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/tf-a-ffa_el3_spmc/include/common/ |
A D | ep_info.h | 20 #define NON_SECURE EP_NON_SECURE macro 21 #define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE))
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/tf-a-ffa_el3_spmc/bl1/ |
A D | bl1_fwu.c | 249 if (GET_SECURITY_STATE(desc->ep_info.h.attr) == NON_SECURE) { in bl1_fwu_image_copy() 531 cm_el1_sysregs_context_save(NON_SECURE); in bl1_fwu_image_execute() 562 if (caller_sec_state == NON_SECURE) { in bl1_fwu_image_resume() 581 resume_sec_state = NON_SECURE; in bl1_fwu_image_resume() 624 if (GET_SECURITY_STATE(flags) == NON_SECURE) { in bl1_fwu_sec_image_done() 655 cm_el1_sysregs_context_restore(NON_SECURE); in bl1_fwu_sec_image_done() 658 cm_set_next_eret_context(NON_SECURE); in bl1_fwu_sec_image_done() 660 *handle = cm_get_context(NON_SECURE); in bl1_fwu_sec_image_done() 663 cm_set_next_context(cm_get_context(NON_SECURE)); in bl1_fwu_sec_image_done() 666 smc_set_next_ctx(NON_SECURE); in bl1_fwu_sec_image_done() [all …]
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/tf-a-ffa_el3_spmc/plat/arm/css/sgi/ |
A D | sgi_ras.c | 123 cm_el1_sysregs_context_save(NON_SECURE); in sgi_ras_intr_handler() 173 cm_el1_sysregs_context_restore(NON_SECURE); in sgi_ras_intr_handler() 174 cm_set_next_eret_context(NON_SECURE); in sgi_ras_intr_handler()
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/tf-a-ffa_el3_spmc/plat/qti/common/src/ |
A D | qti_bl31_setup.c | 129 assert(type == NON_SECURE); in bl31_plat_get_next_image_ep_info() 131 assert(bl33_image_ep_info.h.attr == NON_SECURE); in bl31_plat_get_next_image_ep_info()
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A D | qti_interrupt_svc.c | 57 set_interrupt_rm_flag(flags, NON_SECURE); in qti_interrupt_svc_init()
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/tf-a-ffa_el3_spmc/bl1/tbbr/ |
A D | tbbr_img_desc.c | 26 VERSION_1, entry_point_info_t, NON_SECURE | EXECUTABLE), 57 VERSION_1, entry_point_info_t, NON_SECURE),
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/tf-a-ffa_el3_spmc/plat/xilinx/versal/ |
A D | bl31_versal_setup.c | 37 if (type == NON_SECURE) { in bl31_plat_get_next_image_ep_info() 104 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2() 166 set_interrupt_rm_flag(flags, NON_SECURE); in bl31_plat_runtime_setup()
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/tf-a-ffa_el3_spmc/plat/arm/common/aarch32/ |
A D | arm_bl2_mem_params_desc.c | 60 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), 70 VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
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/tf-a-ffa_el3_spmc/services/std_svc/spm/common/ |
A D | logical_mm_sp.c | 120 cm_el1_sysregs_context_save(NON_SECURE); in spmc_mm_interface_handler() 126 cm_el1_sysregs_context_restore(NON_SECURE); in spmc_mm_interface_handler() 127 cm_set_next_eret_context(NON_SECURE); in spmc_mm_interface_handler() 258 assert(handle == cm_get_context(NON_SECURE)); in handle_ffa_direct_request()
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/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
A D | bl31_plat_setup.c | 159 next_image_info = (type == NON_SECURE) ? in bl31_plat_get_next_image_ep_info() 230 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2() 366 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); in bl31_plat_get_next_kernel64_ep_info() 412 SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); in bl31_plat_get_next_kernel32_ep_info() 431 image_type = NON_SECURE; in bl31_prepare_kernel_entry()
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/tf-a-ffa_el3_spmc/plat/arm/common/aarch64/ |
A D | arm_bl2_mem_params_desc.c | 88 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), 171 VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), 193 VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE),
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A D | execution_state_switch.c | 157 | NON_SECURE | EP_ST_DISABLE)); in arm_execution_state_switch() 165 cm_prepare_el3_exit(NON_SECURE); in arm_execution_state_switch()
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/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/ |
A D | bl31_zynqmp_setup.c | 40 if (type == NON_SECURE) { in bl31_plat_get_next_image_ep_info() 105 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2() 226 set_interrupt_rm_flag(flags, NON_SECURE); in bl31_plat_runtime_setup()
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/tf-a-ffa_el3_spmc/plat/socionext/uniphier/ |
A D | uniphier_image_desc.c | 33 NON_SECURE | NON_EXECUTABLE), 87 NON_SECURE | EXECUTABLE),
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/tf-a-ffa_el3_spmc/plat/marvell/armada/common/ |
A D | marvell_bl31_setup.c | 49 next_image_info = (type == NON_SECURE) in bl31_plat_get_next_image_ep_info() 99 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in marvell_bl31_early_platform_setup()
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/tf-a-ffa_el3_spmc/plat/allwinner/common/ |
A D | sunxi_bl31_setup.c | 104 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); in bl31_early_platform_setup2() 192 if (type == NON_SECURE) in bl31_plat_get_next_image_ep_info()
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