| /tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/ |
| A D | plat.ld.S | 19 ASSERT(. == ALIGN(PAGE_SIZE),
32 .incbin_sram : ALIGN(PAGE_SIZE) {
36 . = ALIGN(PAGE_SIZE);
42 .text_sram : ALIGN(PAGE_SIZE) {
47 . = ALIGN(PAGE_SIZE);
53 .data_sram : ALIGN(PAGE_SIZE) {
57 . = ALIGN(PAGE_SIZE);
63 .stack_sram : ALIGN(PAGE_SIZE) {
65 . += PAGE_SIZE;
|
| /tf-a-ffa_el3_spmc/plat/rockchip/rk3288/include/ |
| A D | plat_sp_min.ld.S | 19 ASSERT(. == ALIGN(PAGE_SIZE),
22 .text_sram : ALIGN(PAGE_SIZE) {
27 . = ALIGN(PAGE_SIZE);
33 .data_sram : ALIGN(PAGE_SIZE) {
37 . = ALIGN(PAGE_SIZE);
43 .stack_sram : ALIGN(PAGE_SIZE) {
45 . += PAGE_SIZE;
|
| /tf-a-ffa_el3_spmc/bl31/ |
| A D | bl31.ld.S | 31 ASSERT(. == ALIGN(PAGE_SIZE),
42 . = ALIGN(PAGE_SIZE);
56 . = ALIGN(PAGE_SIZE);
79 . = ALIGN(PAGE_SIZE);
100 spm_shim_exceptions : ALIGN(PAGE_SIZE) {
103 . = ALIGN(PAGE_SIZE);
129 . = ALIGN(PAGE_SIZE);
136 ASSERT(. == ALIGN(PAGE_SIZE),
153 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
168 . = ALIGN(PAGE_SIZE);
|
| /tf-a-ffa_el3_spmc/bl2/ |
| A D | bl2_el3.ld.S | 31 ASSERT(. == ALIGN(PAGE_SIZE),
35 ASSERT(. == ALIGN(PAGE_SIZE),
48 . = ALIGN(PAGE_SIZE);
58 . = ALIGN(PAGE_SIZE);
62 ASSERT(__TEXT_RESIDENT_END__ - __TEXT_RESIDENT_START__ <= PAGE_SIZE,
83 . = ALIGN(PAGE_SIZE);
94 ASSERT(BL2_RW_BASE == ALIGN(PAGE_SIZE),
120 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
129 . = ALIGN(PAGE_SIZE);
|
| A D | bl2.ld.S | 22 ASSERT(. == ALIGN(PAGE_SIZE),
31 . = ALIGN(PAGE_SIZE);
50 . = ALIGN(PAGE_SIZE);
69 . = ALIGN(PAGE_SIZE);
92 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
101 . = ALIGN(PAGE_SIZE);
|
| /tf-a-ffa_el3_spmc/bl32/tsp/ |
| A D | tsp.ld.S | 23 ASSERT(. == ALIGN(PAGE_SIZE),
32 . = ALIGN(PAGE_SIZE);
42 . = ALIGN(PAGE_SIZE);
62 . = ALIGN(PAGE_SIZE);
91 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
100 . = ALIGN(PAGE_SIZE);
|
| /tf-a-ffa_el3_spmc/bl2u/ |
| A D | bl2u.ld.S | 24 ASSERT(. == ALIGN(PAGE_SIZE),
33 . = ALIGN(PAGE_SIZE);
52 . = ALIGN(PAGE_SIZE);
71 . = ALIGN(PAGE_SIZE);
94 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
103 . = ALIGN(PAGE_SIZE);
|
| /tf-a-ffa_el3_spmc/include/lib/xlat_tables/aarch64/ |
| A D | xlat_tables_aarch64.h | 14 #if !defined(PAGE_SIZE)
33 #if PAGE_SIZE == PAGE_SIZE_4KB
35 #elif (PAGE_SIZE == PAGE_SIZE_16KB) || (PAGE_SIZE == PAGE_SIZE_64KB)
|
| /tf-a-ffa_el3_spmc/bl32/sp_min/ |
| A D | sp_min.ld.S | 25 ASSERT(. == ALIGN(PAGE_SIZE),
34 . = ALIGN(PAGE_SIZE);
57 . = ALIGN(PAGE_SIZE);
81 . = ALIGN(PAGE_SIZE);
114 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
129 . = ALIGN(PAGE_SIZE);
|
| /tf-a-ffa_el3_spmc/include/plat/arm/common/ |
| A D | arm_tzc_dram.ld.S | 18 ASSERT(. == ALIGN(PAGE_SIZE),
20 el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) {
25 . = ALIGN(PAGE_SIZE);
|
| A D | arm_reclaim_init.ld.S | 13 . = ALIGN(PAGE_SIZE);
17 INIT_CODE_END_ALIGNED = ALIGN(PAGE_SIZE);
40 . = ALIGN(PAGE_SIZE); \
|
| A D | arm_spm_def.h | 37 PAGE_SIZE)
57 PAGE_SIZE)
71 PAGE_SIZE)
94 PAGE_SIZE)
|
| /tf-a-ffa_el3_spmc/include/plat/common/ |
| A D | common_def.h | 71 #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE)
75 #define BL2_RO_DATA_END round_up(BL2_ROM_END, PAGE_SIZE)
80 #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE)
84 #define BL2_CODE_END round_up(BL2_ROM_END, PAGE_SIZE)
|
| /tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
| A D | bl31.ld.S | 33 ASSERT(. == ALIGN(PAGE_SIZE),
49 . = ALIGN(PAGE_SIZE);
83 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
98 . = ALIGN(PAGE_SIZE);
|
| /tf-a-ffa_el3_spmc/bl1/ |
| A D | bl1.ld.S | 30 ASSERT(. == ALIGN(PAGE_SIZE),
39 . = ALIGN(PAGE_SIZE);
95 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
113 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
122 . = ALIGN(PAGE_SIZE);
|
| /tf-a-ffa_el3_spmc/include/lib/xlat_tables/aarch32/ |
| A D | xlat_tables_aarch32.h | 14 #if !defined(PAGE_SIZE)
27 #if PAGE_SIZE != PAGE_SIZE_4KB
|
| /tf-a-ffa_el3_spmc/plat/socionext/synquacer/include/ |
| A D | platform_def.h | 102 MT_USER, PAGE_SIZE)
110 MT_USER, PAGE_SIZE)
120 MT_USER, PAGE_SIZE)
130 MT_USER, PAGE_SIZE)
|
| A D | plat.ld.S | 26 sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) {
|
| /tf-a-ffa_el3_spmc/plat/arm/common/ |
| A D | arm_bl31_setup.c | 56 #define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
57 ~(PAGE_SIZE - 1))
58 #define BL_STACKS_END ((BL_STACKS_END_UNALIGNED + PAGE_SIZE - 1) & \
59 ~(PAGE_SIZE - 1))
136 PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE; in arm_bl31_early_platform_setup()
|
| /tf-a-ffa_el3_spmc/plat/socionext/synquacer/ |
| A D | sq_xlat_setup.c | 28 round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE, in sq_mmap_setup()
35 round_up(BL_RO_DATA_END, PAGE_SIZE) - BL_RO_DATA_BASE, in sq_mmap_setup()
|
| /tf-a-ffa_el3_spmc/plat/socionext/uniphier/ |
| A D | uniphier_xlat_setup.c | 42 round_up(BL_END, PAGE_SIZE) - BL_CODE_BASE, in uniphier_mmap_setup()
49 round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE, in uniphier_mmap_setup()
|
| /tf-a-ffa_el3_spmc/plat/arm/board/corstone700/common/include/ |
| A D | platform_def.h | 77 #define BL32_BASE (ARM_BL_RAM_BASE + PAGE_SIZE)
93 #define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
100 + (PAGE_SIZE / 2U))
106 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
|
| /tf-a-ffa_el3_spmc/plat/arm/board/fvp_ve/include/ |
| A D | platform_def.h | 185 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
186 + (PAGE_SIZE / 2U))
192 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
225 + (PAGE_SIZE / 2U))
|
| /tf-a-ffa_el3_spmc/plat/common/ |
| A D | plat_spmd_manifest.c | 135 mapped_size = PAGE_SIZE; in plat_spm_core_manifest_load()
150 PAGE_SIZE, in plat_spm_core_manifest_load()
182 unmap_ret = mmap_remove_dynamic_region(pm_base_align, PAGE_SIZE); in plat_spm_core_manifest_load()
|
| /tf-a-ffa_el3_spmc/plat/qemu/qemu_sbsa/include/ |
| A D | platform_def.h | 285 PAGE_SIZE)
305 PAGE_SIZE)
323 PAGE_SIZE)
345 PAGE_SIZE)
|