Searched refs:PLAT_ARM_GICR_BASE (Results 1 – 17 of 17) sorted by relevance
59 PLAT_ARM_GICR_BASE,61 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1),64 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2),68 PLAT_ARM_GICR_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3),
20 #define PLAT_ARM_GICR_BASE GICR_BASE macro27 #ifndef PLAT_ARM_GICR_BASE28 #define PLAT_ARM_GICR_BASE SMC_UNK macro74 return PLAT_ARM_GICR_BASE; in trusty_get_reg_base()
36 PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */37 PLAT_ARM_GICR_BASE +
79 #define PLAT_ARM_GICR_BASE UL(0x30100000) macro81 #define PLAT_ARM_GICR_BASE UL(0x301C0000) macro
44 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
43 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
47 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
63 #define PLAT_ARM_GICR_BASE UL(0x30140000) macro
58 #define PLAT_ARM_GICR_BASE UL(0x30140000) macro
72 PLAT_ARM_GICR_BASE,73 PLAT_ARM_GICR_BASE + PLAT_ARM_REMOTE_CHIP_OFFSET,
94 #define PLAT_ARM_GICR_BASE UL(0x300C0000) macro
137 #define PLAT_ARM_GICR_BASE 0x300C0000 macro
42 #define PLAT_ARM_GICR_BASE 0x300C0000 macro
124 fvp_gicr_base_addrs[0] = PLAT_ARM_GICR_BASE; in plat_arm_gic_driver_init()
33 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
223 #define PLAT_ARM_GICR_BASE UL(0x30080000) macro
285 #define PLAT_ARM_GICR_BASE BASE_GICR_BASE macro
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