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Searched refs:PLAT_MAX_PWR_LVL (Results 1 – 25 of 108) sorted by relevance

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/tf-a-ffa_el3_spmc/plat/imx/common/
A Dimx8_psci.c39 if (pwr_lvl > PLAT_MAX_PWR_LVL) in imx_validate_power_state()
58 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
60 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/tf-a-ffa_el3_spmc/plat/arm/css/common/
A Dcss_pm.c38 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1
51 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
58 CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
275 assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL); in css_get_sys_suspend_power_state()
277 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) in css_get_sys_suspend_power_state()
306 #if (PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL) in css_validate_power_state()
/tf-a-ffa_el3_spmc/plat/rockchip/common/
A Dplat_pm.c26 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
141 if (pwr_lvl > PLAT_MAX_PWR_LVL) in rockchip_validate_power_state()
160 for (i = (pwr_lvl + 1); i <= PLAT_MAX_PWR_LVL; i++) in rockchip_validate_power_state()
176 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rockchip_get_sys_suspend_power_state()
231 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_off()
267 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend()
288 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_on_finish()
332 for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { in rockchip_pwr_domain_suspend_finish()
/tf-a-ffa_el3_spmc/lib/psci/
A Dpsci_setup.c99 unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; in psci_update_pwrlvl_limits()
100 unsigned int temp_index[PLAT_MAX_PWR_LVL]; in psci_update_pwrlvl_limits()
104 PLAT_MAX_PWR_LVL, in psci_update_pwrlvl_limits()
106 for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { in psci_update_pwrlvl_limits()
129 int level = (int)PLAT_MAX_PWR_LVL; in populate_power_domain_tree()
230 psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL); in psci_setup()
A Dpsci_common.c45 psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT];
75 CASSERT((PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL) &&
76 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
197 pwrlvl = PLAT_MAX_PWR_LVL; in get_power_on_target_pwrlvl()
212 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_set_req_local_pwr_state()
227 for (pwrlvl = 0U; pwrlvl < PLAT_MAX_PWR_LVL; pwrlvl++) { in psci_init_req_local_pwr_states()
248 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_get_req_local_pwr_states()
321 for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_get_target_local_pwr_states()
428 assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); in psci_do_state_coordination()
550 for (i = (int) PLAT_MAX_PWR_LVL; i >= (int) PSCI_CPU_PWR_LVL; i--) { in psci_find_max_off_lvl()
[all …]
A Dpsci_off.c26 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_set_power_off_state()
48 unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0}; in psci_do_cpu_off()
A Dpsci_main.c176 if (psci_find_target_suspend_lvl(&state_info) < PLAT_MAX_PWR_LVL) in psci_system_suspend()
183 state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]) != 0); in psci_system_suspend()
191 PLAT_MAX_PWR_LVL, in psci_system_suspend()
201 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; in psci_cpu_off()
321 if (power_level > PLAT_MAX_PWR_LVL) in psci_node_hw_state()
/tf-a-ffa_el3_spmc/plat/intel/soc/common/
A Dsocfpga_psci.c60 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_off()
76 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend()
92 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_on_finish()
115 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in socfpga_pwr_domain_suspend_finish()
/tf-a-ffa_el3_spmc/plat/arm/common/
A Darm_pm.c33 if (pwr_lvl > PLAT_MAX_PWR_LVL) in arm_validate_power_state()
141 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); in arm_system_pwr_domain_save()
170 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); in arm_system_pwr_domain_resume()
/tf-a-ffa_el3_spmc/services/spd/tlkd/
A Dtlkd_pm.c50 if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) in cpu_suspend_handler()
83 if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) in cpu_resume_handler()
/tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/
A Dplat_psci.c57 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in zynqmp_pwr_domain_off()
81 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in zynqmp_pwr_domain_suspend()
100 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in zynqmp_pwr_domain_on_finish()
112 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in zynqmp_pwr_domain_suspend_finish()
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mq/
A Dimx8mq_psci.c26 if (pwr_lvl > PLAT_MAX_PWR_LVL) in imx_validate_power_state()
102 for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
105 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; in imx_get_sys_suspend_power_state()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8173/
A Dplat_pm.c39 #define MTK_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) ?\
59 #if PLAT_MAX_PWR_LVL > MTK_PWR_LVL1
378 if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && in plat_power_domain_on_finish()
387 if ((PLAT_MAX_PWR_LVL > MTK_PWR_LVL1) && in plat_power_domain_on_finish()
436 assert(PLAT_MAX_PWR_LVL >= 2); in plat_get_sys_suspend_power_state()
438 for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in plat_get_sys_suspend_power_state()
478 if (pwr_lvl > PLAT_MAX_PWR_LVL) in plat_validate_power_state()
548 assert(PLAT_MAX_PWR_LVL >= MTK_PWR_LVL2); in mtk_system_pwr_domain_resume()
/tf-a-ffa_el3_spmc/plat/xilinx/versal/
A Dplat_psci.c56 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in versal_pwr_domain_suspend()
92 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in versal_pwr_domain_suspend_finish()
157 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) in versal_pwr_domain_off()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/
A Dtegra_pm.c40 for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in tegra_get_sys_suspend_power_state()
138 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == in tegra_pwr_domain_power_down_wfi()
161 if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == in tegra_pwr_domain_on_finish()
/tf-a-ffa_el3_spmc/plat/allwinner/common/
A Dsunxi_topology.c12 static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = {
A Dsunxi_scpi_pm.c144 if (power_level > PLAT_MAX_PWR_LVL) { in sunxi_validate_power_state()
170 for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_validate_power_state()
181 for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) { in sunxi_get_sys_suspend_power_state()
/tf-a-ffa_el3_spmc/plat/renesas/common/
A Dplat_pm.c35 #define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
273 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
279 req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSCI_LOCAL_STATE_RUN; in rcar_get_sys_suspend_power_state()
280 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
/tf-a-ffa_el3_spmc/plat/arm/board/sgi575/include/
A Dplatform_def.h28 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 macro
/tf-a-ffa_el3_spmc/plat/arm/board/rde1edge/include/
A Dplatform_def.h25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 macro
/tf-a-ffa_el3_spmc/plat/arm/board/rdn1edge/include/
A Dplatform_def.h28 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 macro
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/
A Dhikey_pm.c28 ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
167 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey_get_sys_suspend_power_state()
223 if (pwr_lvl > PLAT_MAX_PWR_LVL) in hikey_validate_power_state()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey/include/
A Dplatform_def.h35 #define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2) macro
/tf-a-ffa_el3_spmc/plat/imx/imx8m/include/
A Dimx8m_psci.h12 #define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
/tf-a-ffa_el3_spmc/plat/amlogic/g12a/include/
A Dplatform_def.h27 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 macro

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