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Searched refs:PLAT_SQ_MHU_BASE (Results 1 – 3 of 3) sorted by relevance

/tf-a-ffa_el3_spmc/plat/socionext/synquacer/drivers/mhu/
A Dsq_mhu.c44 while (mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_start()
52 assert(!(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) & in mhu_secure_message_send()
56 mmio_write_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); in mhu_secure_message_send()
64 while (!(response = mmio_read_32(PLAT_SQ_MHU_BASE + SCP_INTR_S_STAT))) in mhu_secure_message_wait()
78 mmio_write_32(PLAT_SQ_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); in mhu_secure_message_end()
92 assert(mmio_read_32(PLAT_SQ_MHU_BASE + CPU_INTR_S_STAT) == 0); in mhu_secure_init()
/tf-a-ffa_el3_spmc/plat/socionext/synquacer/include/
A Dplatform_def.h82 #define PLAT_SQ_MHU_BASE 0x45000000 macro
/tf-a-ffa_el3_spmc/plat/socionext/synquacer/drivers/scp/
A Dsq_scmi.c39 .db_reg_addr = PLAT_SQ_MHU_BASE + MHU_CPU_INTR_S_SET_OFFSET,

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