Searched refs:PMCR (Results 1 – 8 of 8) sorted by relevance
| /tf-a-ffa_el3_spmc/docs/perf/ |
| A D | performance-monitoring-unit.rst | 50 ``PMCR`` registers. These can be accessed at all privilege levels.
64 | ``PMCR_EL0[63*:0]`` | ``PMCR[31:0]`` |
129 For ``PMCR``/``PMCR_EL0``, the most important fields are:
145 - The effects of ``PMCNTENSET`` and ``PMCR.DP`` are applied on top of this.
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| /tf-a-ffa_el3_spmc/include/arch/aarch32/ |
| A D | smccc_macros.S | 101 ldcopr r5, PMCR
112 stcopr r5, PMCR
162 stcopr r1, PMCR
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| A D | el3_common_macros.S | 152 stcopr r0, PMCR
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| A D | arch_helpers.h | 287 DEFINE_COPROCR_READ_FUNC(pmcr, PMCR) in DEFINE_SYSREG_RW_FUNCS()
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| A D | arch.h | 557 #define PMCR p15, 0, c9, c12, 0 macro
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| /tf-a-ffa_el3_spmc/docs/security_advisories/ |
| A D | security-advisory-tfv-5.rst | 47 The same issue exists for the equivalent AArch32 register, ``PMCR``, except that
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| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | security-hardening.rst | 42 Since the Non-secure world has access to the ``PMCR`` register, it can
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| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 2127 CPU cold/warm boot. For the earlier architectures PMCR register is
2129 and cycle counting gets disabled by setting PMCR.DP bit.
3141 - Control register PMCR_EL0 / PMCR is set to prohibit cycle counting in the
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