Searched refs:RCC_BDCR (Results 1 – 3 of 3) sorted by relevance
| /tf-a-ffa_el3_spmc/plat/st/stm32mp1/ |
| A D | bl2_plat_setup.c | 211 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { in bl2_el3_plat_arch_setup()
212 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
214 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == in bl2_el3_plat_arch_setup()
219 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
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| /tf-a-ffa_el3_spmc/drivers/st/clk/ |
| A D | stm32mp1_clk.c | 412 _CLK_SELEC(RCC_BDCR, 20, RTC, _RTC_SEL),
506 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents),
1237 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); in stm32mp1_lse_enable()
1241 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
1248 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> in stm32mp1_lse_enable()
1258 mmio_clrsetbits_32(rcc_base + RCC_BDCR, in stm32mp1_lse_enable()
1263 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); in stm32mp1_lse_enable()
1268 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { in stm32mp1_lse_wait()
1649 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; in stm32mp1_set_rtcsrc()
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| /tf-a-ffa_el3_spmc/include/drivers/st/ |
| A D | stm32mp1_rcc.h | 49 #define RCC_BDCR U(0x140) macro
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