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Searched refs:RCC_SELR_SRC_MASK (Results 1 – 2 of 2) sorted by relevance

/tf-a-ffa_el3_spmc/drivers/st/clk/
A Dstm32mp1_clk.c835 switch (reg & RCC_SELR_SRC_MASK) { in get_clock_rate()
865 switch (reg & RCC_SELR_SRC_MASK) { in get_clock_rate()
902 switch (reg & RCC_SELR_SRC_MASK) { in get_clock_rate()
943 switch (reg & RCC_SELR_SRC_MASK) { in get_clock_rate()
1387 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; in stm32mp1_check_pll_conf()
1388 if (src != (clksrc & RCC_SELR_SRC_MASK)) { in stm32mp1_check_pll_conf()
1590 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, in stm32mp1_set_clksrc()
1591 clksrc & RCC_SELR_SRC_MASK); in stm32mp1_set_clksrc()
/tf-a-ffa_el3_spmc/include/drivers/st/
A Dstm32mp1_rcc.h244 #define RCC_SELR_SRC_MASK GENMASK(2, 0) macro

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