Searched refs:REG_WMSK_BITS (Results 1 – 2 of 2) sorted by relevance
| /tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/soc/ |
| A D | soc.h | 101 #define PLL_PWR_DN REG_WMSK_BITS(1, 1, 0x1)
102 #define PLL_PWR_ON REG_WMSK_BITS(0, 1, 0x1)
103 #define PLL_RESET REG_WMSK_BITS(1, 5, 0x1)
104 #define PLL_RESET_RESUME REG_WMSK_BITS(0, 5, 0x1)
107 #define PLL_BYPASS REG_WMSK_BITS(1, 0, 0x1)
108 #define PLL_NO_BYPASS REG_WMSK_BITS(0, 0, 0x1)
115 #define PLL_SLOW_BITS REG_WMSK_BITS(PLL_SLOW, 8, 0x3)
116 #define PLL_NORM_BITS REG_WMSK_BITS(PLL_NORM, 8, 0x3)
117 #define PLL_DEEP_BITS REG_WMSK_BITS(PLL_DEEP, 8, 0x3)
127 #define REG_WMSK_BITS(bits, bits_shift, msk) \ macro
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/soc/ |
| A D | soc.h | 67 #define PLL_PWR_DN REG_WMSK_BITS(1, 1, 0x1)
68 #define PLL_PWR_ON REG_WMSK_BITS(0, 1, 0x1)
69 #define PLL_RESET REG_WMSK_BITS(1, 5, 0x1)
70 #define PLL_RESET_RESUME REG_WMSK_BITS(0, 5, 0x1)
73 #define PLL_BYPASS REG_WMSK_BITS(1, 0, 0x1)
74 #define PLL_NO_BYPASS REG_WMSK_BITS(0, 0, 0x1)
91 #define REG_WMSK_BITS(bits, bits_shift, msk) \ macro
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