Searched refs:SCR (Results 1 – 8 of 8) sorted by relevance
| /tf-a-ffa_el3_spmc/include/arch/aarch32/ |
| A D | smccc_macros.S | 27 ldcopr r4, SCR
29 stcopr r2, SCR
60 stcopr r4, SCR
86 ldcopr r4, SCR
136 stcopr r1, SCR
169 ldcopr r4, SCR
171 stcopr r2, SCR
201 stcopr r4, SCR
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| A D | el3_common_macros.S | 47 stcopr r0, SCR
220 ldcopr r0, SCR
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| A D | arch_helpers.h | 226 DEFINE_COPROCR_RW_FUNCS(scr, SCR) in DEFINE_SYSREG_RW_FUNCS()
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| A D | arch.h | 499 #define SCR p15, 0, c1, c1, 0 macro
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| /tf-a-ffa_el3_spmc/bl32/sp_min/aarch32/ |
| A D | entrypoint.S | 34 ldcopr \reg, SCR
37 stcopr \reg, SCR
221 stcopr r0, SCR
265 stcopr r0, SCR
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| /tf-a-ffa_el3_spmc/bl1/aarch32/ |
| A D | bl1_exceptions.S | 41 ldcopr r8, SCR
110 stcopr r0, SCR
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| /tf-a-ffa_el3_spmc/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 102 #. Values for certain system registers like SCR and SCTLR cannot be
114 registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
156 for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | firmware-design.rst | 247 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
248 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
276 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
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