SCR_FIQ_BIT (reference) in projects: tf-a-ffa_el3_spmc

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Searched refs:SCR_FIQ_BIT (Results 1 – 21 of 21) sorted by relevance

/tf-a-ffa_el3_spmc/plat/imx/imx8m/
A D	imx8m_psci_common.c	`93 write_scr_el3(read_scr_el3() \| SCR_FIQ_BIT); in imx_cpu_standby() 98 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_cpu_standby() 114 write_scr_el3(read_scr_el3() \| SCR_FIQ_BIT); in imx_domain_suspend() 142 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_domain_suspend_finish()`
/tf-a-ffa_el3_spmc/plat/common/
A D	plat_gicv3.c	`161 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line() 169 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line() 178 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line()`
A D	plat_gicv2.c	`149 return ((gicv2_is_fiq_enabled() != 0U) ? __builtin_ctz(SCR_FIQ_BIT) : in plat_interrupt_type_to_line()`
/tf-a-ffa_el3_spmc/plat/imx/imx8qx/
A D	imx8qx_psci.c	`123 write_scr_el3(read_scr_el3() \| SCR_FIQ_BIT); in imx_domain_suspend() 211 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_domain_suspend_finish()`
/tf-a-ffa_el3_spmc/plat/imx/imx8m/imx8mq/
A D	imx8mq_psci.c	`55 write_scr_el3(read_scr_el3() \| SCR_FIQ_BIT); in imx_domain_suspend()`
/tf-a-ffa_el3_spmc/plat/rpi/common/
A D	rpi3_common.c	`246 return __builtin_ctz(SCR_FIQ_BIT); in plat_interrupt_type_to_line()`
/tf-a-ffa_el3_spmc/drivers/renesas/common/watchdog/
A D	swdt.c	`143 write_scr_el3(read_scr_el3() & ~SCR_FIQ_BIT); in rcar_swdt_release()`
/tf-a-ffa_el3_spmc/plat/imx/imx8qm/
A D	imx8qm_psci.c	`149 write_scr_el3(read_scr_el3() \| SCR_FIQ_BIT); in imx_domain_suspend() 278 write_scr_el3(read_scr_el3() & (~SCR_FIQ_BIT)); in imx_domain_suspend_finish()`
/tf-a-ffa_el3_spmc/plat/ti/k3/common/
A D	k3_psci.c	`32 write_scr_el3(scr \| SCR_IRQ_BIT \| SCR_FIQ_BIT); in k3_cpu_standby()`
/tf-a-ffa_el3_spmc/plat/arm/css/common/
A D	css_pm.c	`252 write_scr_el3(scr \| SCR_IRQ_BIT \| SCR_FIQ_BIT); in css_cpu_standby()`
/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/
A D	brcm_pm_ops.c	`206 write_scr_el3(scr \| SCR_IRQ_BIT \| SCR_FIQ_BIT); in brcm_cpu_standby()`
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/
A D	hikey960_pm.c	`47 write_scr_el3(scr \| SCR_IRQ_BIT \| SCR_FIQ_BIT); in hikey960_pwr_domain_standby()`
/tf-a-ffa_el3_spmc/bl32/sp_min/aarch32/
A D	entrypoint.S	`35 orr \reg, \reg, #SCR_FIQ_BIT`
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/
A D	plat_pm.c	`186 write_scr_el3(scr \| SCR_IRQ_BIT \| SCR_FIQ_BIT); in plat_cpu_standby()`
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/
A D	plat_pm.c	`181 write_scr_el3(scr \| SCR_IRQ_BIT \| SCR_FIQ_BIT); in plat_cpu_standby()`
/tf-a-ffa_el3_spmc/lib/el3_runtime/aarch64/
A D	context_mgmt.c	`91 scr_el3 &= ~(SCR_NS_BIT \| SCR_RW_BIT \| SCR_FIQ_BIT \| SCR_IRQ_BIT \| in cm_setup_context()`
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/
A D	plat_pm.c	`203 write_scr_el3(scr \| SCR_IRQ_BIT \| SCR_FIQ_BIT); in plat_cpu_standby()`
/tf-a-ffa_el3_spmc/plat/renesas/rzg/
A D	bl2_plat_setup.c	`704 write_scr_el3(read_scr_el3() \| SCR_FIQ_BIT); in bl2_el3_early_platform_setup()`
/tf-a-ffa_el3_spmc/plat/renesas/rcar/
A D	bl2_plat_setup.c	`840 write_scr_el3(read_scr_el3() \| SCR_FIQ_BIT); in bl2_el3_early_platform_setup()`
/tf-a-ffa_el3_spmc/include/arch/aarch32/
A D	arch.h	`212 #define SCR_FIQ_BIT (UL(1) << 2) macro`
/tf-a-ffa_el3_spmc/include/arch/aarch64/
A D	arch.h	`435 #define SCR_FIQ_BIT (UL(1) << 2) macro`

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