Searched refs:SDCR (Results 1 – 8 of 8) sorted by relevance
| /tf-a-ffa_el3_spmc/lib/extensions/mtpmu/aarch32/ |
| A D | mtpmu.S | 79 ldcopr r0, SDCR
82 stcopr r0, SDCR
|
| /tf-a-ffa_el3_spmc/include/arch/aarch32/ |
| A D | smccc_macros.S | 95 ldcopr r5, SDCR
154 ldcopr r1, SDCR
|
| A D | el3_common_macros.S | 125 stcopr r0, SDCR
|
| A D | arch.h | 502 #define SDCR p15, 0, c1, c3, 1 macro
|
| /tf-a-ffa_el3_spmc/docs/security_advisories/ |
| A D | security-advisory-tfv-2.rst | 54 macro. Here the affected bits are ``SDCR.SPD``, which should also be assigned to
|
| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | security-hardening.rst | 117 In Aarch32 execution state the ``MDCR_EL3`` alias is the ``SDCR`` register,
|
| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | firmware-design.rst | 293 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
|
| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 2126 For ARMv8.5 the counter gets disabled by setting ``SDCR.SCCD`` bit on
3466 - Debug registers MDCR-EL3/SDCR and MDCR_EL2/HDCR are initialised to avoid
|
Completed in 18 milliseconds