Home
last modified time | relevance | path

Searched refs:SPM_MP0_CPUTOP_PWR_CON (Results 1 – 5 of 5) sorted by relevance

/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc_private.h69 #define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204) macro
95 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
A Dmtspmc.c110 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc_private.h69 #define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204) macro
95 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
A Dmtspmc.c102 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
/tf-a-ffa_el3_spmc/plat/mediatek/mt8183/drivers/spmc/
A Dmtspmc_private.h35 #define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) macro
113 [0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },

Completed in 7 milliseconds