1 /*
2  * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef RK3328_DEF_H
8 #define RK3328_DEF_H
9 
10 #define MAJOR_VERSION		(1)
11 #define MINOR_VERSION		(2)
12 
13 #define SIZE_K(n)		((n) * 1024)
14 
15 /* Special value used to verify platform parameters from BL2 to BL3-1 */
16 #define RK_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
17 
18 #define UART0_BASE		0xff110000
19 #define UART0_SIZE		SIZE_K(64)
20 
21 #define UART1_BASE		0xff120000
22 #define UART1_SIZE		SIZE_K(64)
23 
24 #define UART2_BASE		0xff130000
25 #define UART2_SIZE		SIZE_K(64)
26 
27 #define PMU_BASE		0xff140000
28 #define PMU_SIZE		SIZE_K(64)
29 
30 #define SGRF_BASE		0xff0d0000
31 #define SGRF_SIZE		SIZE_K(64)
32 
33 #define CRU_BASE		0xff440000
34 #define CRU_SIZE		SIZE_K(64)
35 
36 #define GRF_BASE		0xff100000
37 #define GRF_SIZE		SIZE_K(64)
38 
39 #define GPIO0_BASE		0xff210000
40 #define GPIO0_SIZE		SIZE_K(32)
41 
42 #define GPIO1_BASE		0xff220000
43 #define GPIO1_SIZE		SIZE_K(32)
44 
45 #define GPIO2_BASE		0xff230000
46 #define GPIO2_SIZE		SIZE_K(64)
47 
48 #define GPIO3_BASE		0xff240000
49 #define GPIO3_SIZE		SIZE_K(64)
50 
51 #define STIME_BASE		0xff1d0000
52 #define STIME_SIZE		SIZE_K(64)
53 
54 #define INTMEM_BASE		0xff090000
55 #define INTMEM_SIZE		SIZE_K(32)
56 
57 #define SRAM_LDS_BASE		(INTMEM_BASE + SIZE_K(4))
58 #define SRAM_LDS_SIZE		(INTMEM_SIZE - SIZE_K(4))
59 
60 #define PMUSRAM_BASE		INTMEM_BASE
61 #define PMUSRAM_SIZE		SIZE_K(4)
62 #define PMUSRAM_RSIZE		SIZE_K(4)
63 
64 #define VOP_BASE		0xff370000
65 #define VOP_SIZE		SIZE_K(16)
66 
67 #define DDR_PHY_BASE		0xff400000
68 #define DDR_PHY_SIZE		SIZE_K(4)
69 
70 #define SERVER_MSCH_BASE	0xff720000
71 #define SERVER_MSCH_SIZE	SIZE_K(4)
72 
73 #define DDR_UPCTL_BASE		0xff780000
74 #define DDR_UPCTL_SIZE		SIZE_K(12)
75 
76 #define DDR_MONITOR_BASE	0xff790000
77 #define DDR_MONITOR_SIZE	SIZE_K(4)
78 
79 #define FIREWALL_DDR_BASE	0xff7c0000
80 #define FIREWALL_DDR_SIZE	SIZE_K(64)
81 
82 #define FIREWALL_CFG_BASE	0xff7d0000
83 #define FIREWALL_CFG_SIZE	SIZE_K(64)
84 
85 #define GIC400_BASE		0xff810000
86 #define GIC400_SIZE		SIZE_K(64)
87 
88 #define DDR_GRF_BASE		0xff798000
89 #define DDR_GRF_SIZE		SIZE_K(16)
90 
91 #define PWM_BASE		0xff1b0000
92 #define PWM_SIZE		SIZE_K(64)
93 
94 #define DDR_PARAM_BASE		0x02000000
95 #define DDR_PARAM_SIZE		SIZE_K(4)
96 
97 #define EFUSE8_BASE		0xff260000
98 #define EFUSE8_SIZE		SIZE_K(4)
99 
100 #define EFUSE32_BASE		0xff0b0000
101 #define EFUSE32_SIZE		SIZE_K(4)
102 
103 /**************************************************************************
104  * UART related constants
105  **************************************************************************/
106 #define RK3328_BAUDRATE	1500000
107 #define RK3328_UART_CLOCK	24000000
108 
109 /******************************************************************************
110  * System counter frequency related constants
111  ******************************************************************************/
112 #define SYS_COUNTER_FREQ_IN_TICKS	24000000U
113 #define SYS_COUNTER_FREQ_IN_MHZ		24
114 
115 /******************************************************************************
116  * GIC-400 & interrupt handling related constants
117  ******************************************************************************/
118 
119 /* Base rk_platform compatible GIC memory map */
120 #define RK3328_GICD_BASE		(GIC400_BASE + 0x1000)
121 #define RK3328_GICC_BASE		(GIC400_BASE + 0x2000)
122 #define RK3328_GICR_BASE		0	/* no GICR in GIC-400 */
123 
124 /******************************************************************************
125  * sgi, ppi
126  ******************************************************************************/
127 #define RK_IRQ_SEC_PHY_TIMER	29
128 
129 #define RK_IRQ_SEC_SGI_0	8
130 #define RK_IRQ_SEC_SGI_1	9
131 #define RK_IRQ_SEC_SGI_2	10
132 #define RK_IRQ_SEC_SGI_3	11
133 #define RK_IRQ_SEC_SGI_4	12
134 #define RK_IRQ_SEC_SGI_5	13
135 #define RK_IRQ_SEC_SGI_6	14
136 #define RK_IRQ_SEC_SGI_7	15
137 
138 /*
139  * Define a list of Group 0 interrupts.
140  */
141 #define PLAT_RK_GICV2_G0_IRQS						\
142 	INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,	\
143 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),		\
144 	INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,	\
145 		       GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
146 
147 #define SHARE_MEM_BASE          0x100000/* [1MB, 1MB+60K]*/
148 #define SHARE_MEM_PAGE_NUM      15
149 #define SHARE_MEM_SIZE          SIZE_K(SHARE_MEM_PAGE_NUM * 4)
150 
151 #endif /* RK3328_DEF_H */
152