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Searched refs:STIMER_CHN_BASE (Results 1 – 4 of 4) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/secure/
A Dsecure.c52 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
55 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT0, 0xffffffff); in secure_timer_init()
56 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOAD_COUNT1, 0xffffffff); in secure_timer_init()
59 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
A Dsecure.h42 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.c92 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT0, 0xffffffff); in secure_timer_init()
93 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_LOADE_COUNT1, 0xffffffff); in secure_timer_init()
95 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
A Dsoc.h67 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) macro

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