TEGRA_CL_DVFS_BASE (reference) in projects: tf-a-ffa_el3_spmc

Searched refs:TEGRA_CL_DVFS_BASE (Results 1 – 2 of 2) sorted by relevance

/tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/
A D	plat_psci_handlers.c	`139 val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); in tegra_soc_get_target_pwr_state() 230 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, in tegra_soc_pwr_domain_suspend() 234 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); in tegra_soc_pwr_domain_suspend() 513 cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); in tegra_soc_pwr_domain_on_finish() 528 mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, in tegra_soc_pwr_domain_on_finish()`
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t210/
A D	tegra_def.h	`258 #define TEGRA_CL_DVFS_BASE U(0x70110000) macro`

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