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Searched refs:TEGRA_EVP_BASE (Results 1 – 2 of 2) sorted by relevance

/tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/flowctrl/
A Dflowctrl.c271 mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, entrypoint); in tegra_fc_bpmp_on()
272 while (entrypoint != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) in tegra_fc_bpmp_on()
297 mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, 0); in tegra_fc_bpmp_off()
298 while (0 != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) in tegra_fc_bpmp_off()
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t210/
A Dtegra_def.h185 #define TEGRA_EVP_BASE U(0x6000F000) macro

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