Searched refs:TEGRA_MC_BASE (Results 1 – 11 of 11) sorted by relevance
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/drivers/ |
| A D | memctrl_v2.h | 40 .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
64 return mmio_read_32(TEGRA_MC_BASE + off); in tegra_mc_read_32()
69 mmio_write_32(TEGRA_MC_BASE + off, val); in tegra_mc_write_32()
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| A D | memctrl_v1.h | 49 return mmio_read_32(TEGRA_MC_BASE + off); in tegra_mc_read_32()
54 mmio_write_32(TEGRA_MC_BASE + off, val); in tegra_mc_write_32()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/memctrl/ |
| A D | memctrl_v1.c | 206 mcerr = mmio_read_32(TEGRA_MC_BASE + MC_INTSTATUS); in tegra_memctrl_clear_pending_interrupts()
210 mmio_write_32((TEGRA_MC_BASE + MC_INTSTATUS), mcerr); in tegra_memctrl_clear_pending_interrupts()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/ |
| A D | tegra_sip_calls.c | 56 if (mmio_read_32(TEGRA_MC_BASE + MC_VIDEO_PROTECT_REG_CTRL) in tegra_sip_handler()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/ |
| A D | plat_trampoline.S | 134 mov x0, #TEGRA_MC_BASE
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| A D | plat_setup.c | 95 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t210/ |
| A D | tegra_def.h | 234 #define TEGRA_MC_BASE U(0x70019000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t186/ |
| A D | tegra_def.h | 145 #define TEGRA_MC_BASE U(0x02C10000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t194/ |
| A D | tegra_def.h | 82 #define TEGRA_MC_BASE U(0x02C10000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
| A D | plat_setup.c | 79 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/drivers/se/ |
| A D | security_engine.c | 974 val = mmio_read_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0); in tegra_se_suspend()
976 mmio_write_32(TEGRA_MC_BASE + MC_SMMU_PPCS_ASID_0, val); in tegra_se_suspend()
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Completed in 21 milliseconds