Searched refs:TEGRA_MISC_BASE (Results 1 – 14 of 14) sorted by relevance
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/ |
| A D | plat_secondary.c | 57 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); in plat_secondary_setup()
58 assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW) == addr_low); in plat_secondary_setup()
59 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); in plat_secondary_setup()
60 assert(mmio_read_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH) == addr_high); in plat_secondary_setup()
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| A D | plat_smmu.c | 18 return mmio_read_32((uintptr_t)TEGRA_MISC_BASE + off); in tegra_misc_read_32()
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| A D | plat_setup.c | 89 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
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| A D | plat_psci_handlers.c | 138 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); in tegra_soc_pwr_domain_suspend()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/ |
| A D | plat_setup.c | 246 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in plat_late_platform_setup()
248 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in plat_late_platform_setup()
253 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in plat_late_platform_setup()
255 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in plat_late_platform_setup()
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| A D | plat_psci_handlers.c | 239 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); in tegra_soc_pwr_domain_suspend()
241 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); in tegra_soc_pwr_domain_suspend()
399 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in tegra_soc_pwr_domain_power_down_wfi()
401 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in tegra_soc_pwr_domain_power_down_wfi()
498 val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); in tegra_soc_pwr_domain_on_finish()
500 mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); in tegra_soc_pwr_domain_on_finish()
515 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); in tegra_soc_pwr_domain_on_finish()
517 mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); in tegra_soc_pwr_domain_on_finish()
520 val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); in tegra_soc_pwr_domain_on_finish()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/ |
| A D | tegra_stack_protector.c | 23 seed = mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); in plat_get_stack_protector_canary()
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| A D | tegra_platform.c | 58 return mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET); in tegra_get_chipid()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t210/ |
| A D | tegra_def.h | 190 #define TEGRA_MISC_BASE U(0x70000000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t186/ |
| A D | tegra_def.h | 89 #define TEGRA_MISC_BASE U(0x00100000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t194/ |
| A D | tegra_def.h | 65 #define TEGRA_MISC_BASE U(0x00100000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
| A D | plat_setup.c | 73 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
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| A D | plat_psci_handlers.c | 138 val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); in tegra_soc_pwr_domain_suspend()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/aarch64/ |
| A D | tegra_helpers.S | 307 mov x0, #TEGRA_MISC_BASE
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