Searched refs:TEGRA_SCRATCH_BASE (Results 1 – 12 of 12) sorted by relevance
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/ |
| A D | plat_secondary.c | 63 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, in plat_secondary_setup()
65 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO) == addr_low); in plat_secondary_setup()
66 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, in plat_secondary_setup()
68 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI) == addr_high); in plat_secondary_setup()
69 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO, in plat_secondary_setup()
71 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_LO) == (uint32_t)tzdram_addr); in plat_secondary_setup()
72 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI, in plat_secondary_setup()
74 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV72_HI) == (uint32_t)src_len_bytes); in plat_secondary_setup()
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| A D | plat_setup.c | 125 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
374 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) & in plat_get_bl31_params()
377 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR); in plat_get_bl31_params()
389 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) & in plat_get_bl31_plat_params()
392 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR); in plat_get_bl31_plat_params()
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| A D | plat_psci_handlers.c | 139 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); in tegra_soc_pwr_domain_suspend()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/ |
| A D | plat_secondary.c | 37 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO, in plat_secondary_setup()
39 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI, in plat_secondary_setup()
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| A D | plat_setup.c | 103 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
266 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR); in plat_get_bl31_params()
278 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR); in plat_get_bl31_plat_params()
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| A D | plat_psci_handlers.c | 139 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); in tegra_soc_pwr_domain_suspend()
328 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO, in tegra_soc_pwr_domain_power_down_wfi()
330 mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI, in tegra_soc_pwr_domain_power_down_wfi()
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| A D | plat_memctrl.c | 690 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_LO, val); in plat_memctrl_tzdram_setup()
693 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val); in plat_memctrl_tzdram_setup()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/drivers/memctrl/ |
| A D | memctrl_v2.c | 161 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO, in tegra_mc_save_context()
163 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO) in tegra_mc_save_context()
165 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI, in tegra_mc_save_context()
167 assert(mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI) in tegra_mc_save_context()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/se/ |
| A D | se.c | 269 mmio_write_32(TEGRA_SCRATCH_BASE + scratch_offset, val); in tegra_se_save_sha256_hash()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t186/ |
| A D | tegra_def.h | 261 #define TEGRA_SCRATCH_BASE U(0x0C390000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t194/ |
| A D | tegra_def.h | 218 #define TEGRA_SCRATCH_BASE U(0x0C390000) macro
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t194/drivers/se/ |
| A D | se.c | 401 mmio_write_32((uint32_t)(TEGRA_SCRATCH_BASE + scratch_offset), in tegra_se_save_sha256_pmc_scratch()
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