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Searched refs:TIMER_CONTROL_REG (Results 1 – 10 of 10) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/secure/
A Dsecure.c94 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in sram_secure_timer_init()
100 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in sram_secure_timer_init()
112 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in secure_timer_init()
118 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
A Dsecure.h86 #define TIMER_CONTROL_REG 0x10 macro
/tf-a-ffa_el3_spmc/plat/rockchip/px30/drivers/secure/
A Dsecure.c52 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
59 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, in secure_timer_init()
A Dsecure.h50 #define TIMER_CONTROL_REG 0x10 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/secure/
A Dsecure.c118 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in sram_secure_timer_init()
131 mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, in secure_timer_init()
A Dsecure.h84 #define TIMER_CONTROL_REG 0x1c macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.h15 #define TIMER_CONTROL_REG 0x10 macro
A Dsoc.c95 mmio_write_32(STIMER_CHN_BASE(1) + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/soc/
A Dsoc.h27 #define TIMER_CONTROL_REG 0x10 macro
A Dsoc.c74 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()

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