1 /* 2 * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SECURE_H 8 #define SECURE_H 9 10 /*************************************************************************** 11 * SGRF 12 ***************************************************************************/ 13 #define SGRF_SOC_CON(i) ((i) * 0x4) 14 #define SGRF_DMAC_CON(i) (0x30 + (i) * 0x4) 15 16 #define SGRF_MST_S_ALL_NS 0xffffffff 17 #define SGRF_SLV_S_ALL_NS 0xffff0000 18 #define DMA_IRQ_BOOT_NS 0xffffffff 19 #define DMA_PERI_CH_NS_15_0 0xffffffff 20 #define DMA_PERI_CH_NS_19_16 0x000f000f 21 #define DMA_MANAGER_BOOT_NS 0x00010001 22 #define DMA_SOFTRST_REQ BITS_WITH_WMASK(1, 0x1, 12) 23 #define DMA_SOFTRST_RLS BITS_WITH_WMASK(0, 0x1, 12) 24 25 /*************************************************************************** 26 * DDR FIREWALL 27 ***************************************************************************/ 28 #define FIREWALL_DDR_FW_DDR_RGN(i) ((i) * 0x4) 29 #define FIREWALL_DDR_FW_DDR_MST(i) (0x20 + (i) * 0x4) 30 #define FIREWALL_DDR_FW_DDR_CON_REG 0x40 31 #define FIREWALL_DDR_FW_DDR_RGN_NUM 8 32 #define FIREWALL_DDR_FW_DDR_MST_NUM 6 33 34 #define PLAT_MAX_DDR_CAPACITY_MB 4096 35 #define RG_MAP_SECURE(top, base) ((((top) - 1) << 16) | (base)) 36 37 /************************************************** 38 * secure timer 39 **************************************************/ 40 41 /* chanal0~5 */ 42 #define STIMER_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 43 44 #define TIMER_LOAD_COUNT0 0x0 45 #define TIMER_LOAD_COUNT1 0x4 46 47 #define TIMER_CUR_VALUE0 0x8 48 #define TIMER_CUR_VALUE1 0xc 49 50 #define TIMER_CONTROL_REG 0x10 51 #define TIMER_INTSTATUS 0x18 52 53 #define TIMER_DIS 0x0 54 #define TIMER_EN 0x1 55 56 #define TIMER_FMODE (0x0 << 1) 57 #define TIMER_RMODE (0x1 << 1) 58 59 #define TIMER_LOAD_COUNT0_MSK (0xffffffff) 60 #define TIMER_LOAD_COUNT1_MSK (0xffffffff00000000) 61 62 void secure_timer_init(void); 63 void sgrf_init(void); 64 65 #endif /* SECURE_H */ 66