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Searched refs:TZC_REGION_ACCESS_RDWR (Results 1 – 10 of 10) sorted by relevance

/tf-a-ffa_el3_spmc/plat/st/stm32mp1/
A Dstm32mp1_security.c18 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \
19 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \
20 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \
21 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \
22 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \
23 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \
24 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \
25 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \
26 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \
27 TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \
[all …]
/tf-a-ffa_el3_spmc/plat/arm/board/rdn2/include/
A Dplatform_def.h54 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
55 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
56 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
57 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \
58 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \
59 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
60 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
61 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/tf-a-ffa_el3_spmc/plat/arm/board/rdv1/include/
A Dplatform_def.h42 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
43 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
44 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
45 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
46 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
47 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/tf-a-ffa_el3_spmc/plat/arm/board/rdv1mc/include/
A Dplatform_def.h39 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
40 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
41 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
42 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
43 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
44 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
/tf-a-ffa_el3_spmc/plat/arm/css/sgm/include/
A Dsgm_base_platform_def.h104 TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP) | \
105 TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0) | \
106 TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD1) | \
107 TZC_REGION_ACCESS_RDWR(TZC_NSAID_GPU) | \
108 TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIDEO) | \
109 TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP0) | \
110 TZC_REGION_ACCESS_RDWR(TZC_NSAID_DISP1))
/tf-a-ffa_el3_spmc/plat/arm/board/juno/include/
A Dplatform_def.h215 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \
216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \
217 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \
218 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \
219 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \
220 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \
221 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \
222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \
223 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \
224 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT))
/tf-a-ffa_el3_spmc/plat/arm/board/juno/
A Djuno_tzmp1_def.h54 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE) | \
58 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED))
61 (TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE))
/tf-a-ffa_el3_spmc/plat/arm/board/fvp/include/
A Dplatform_def.h273 TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \
274 TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \
275 TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \
276 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \
277 TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD))
/tf-a-ffa_el3_spmc/include/drivers/arm/
A Dtzc_common.h81 #define TZC_REGION_ACCESS_RDWR(nsaid) \ macro
/tf-a-ffa_el3_spmc/plat/arm/board/tc/include/
A Dplatform_def.h250 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))

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