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Searched refs:UART2_BASE (Results 1 – 15 of 15) sorted by relevance

/tf-a-ffa_el3_spmc/plat/rockchip/px30/
A Dpx30_def.h55 #define UART2_BASE 0xff160000 macro
127 #define PX30_UART_BASE UART2_BASE
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/include/
A Dplatform_def.h90 #define PLAT_RK_UART_BASE UART2_BASE
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/include/
A Dplatform_def.h108 #define PLAT_RK_UART_BASE UART2_BASE
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/
A Dplatform_def.h93 #define PLAT_RK_UART_BASE UART2_BASE
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/
A Drk3368_def.h44 #define UART2_BASE 0xff690000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/include/
A Dplatform_def.h109 #define PLAT_RK_UART_BASE UART2_BASE
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/
A Drk3288_def.h37 #define UART2_BASE 0xff690000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/
A Drk3328_def.h24 #define UART2_BASE 0xff130000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/pmu/
A Dpmu.c559 sram_data.uart2_ier = mmio_read_32(UART2_BASE + UART_IER); in sram_dbg_uart_suspend()
560 mmio_write_32(UART2_BASE + UART_IER, UART_INT_DISABLE); in sram_dbg_uart_suspend()
570 mmio_write_32(UART2_BASE + UART_FCR, UART_FIFO_RESET); in sram_dbg_uart_resume()
571 mmio_write_32(UART2_BASE + UART_IER, sram_data.uart2_ier); in sram_dbg_uart_resume()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/include/shared/
A Daddressmap_shared.h23 #define UART2_BASE (MMIO_BASE + 0x071A0000) macro
/tf-a-ffa_el3_spmc/plat/rockchip/common/
A Dparams_setup.c89 uart_base = UART2_BASE; in plat_rockchip_dt_process_fdt_uart()
/tf-a-ffa_el3_spmc/plat/rockchip/rk3328/drivers/soc/
A Dsoc.c26 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
/tf-a-ffa_el3_spmc/plat/qemu/qemu_sbsa/include/
A Dplatform_def.h186 #define UART2_BASE 0x60040000 macro
/tf-a-ffa_el3_spmc/plat/rockchip/rk3288/drivers/soc/
A Dsoc.c41 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
/tf-a-ffa_el3_spmc/plat/rockchip/rk3368/drivers/soc/
A Dsoc.c37 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,

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