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Searched refs:__COHERENT_RAM_START__ (Results 1 – 15 of 15) sorted by relevance

/tf-a-ffa_el3_spmc/plat/mediatek/mt6795/
A Dbl31.ld.S84 __COHERENT_RAM_START__ = .; define
112 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
/tf-a-ffa_el3_spmc/bl32/tsp/
A Dtsp.ld.S92 __COHERENT_RAM_START__ = .; define
119 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
/tf-a-ffa_el3_spmc/bl2/
A Dbl2.ld.S93 __COHERENT_RAM_START__ = .; define
117 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
A Dbl2_el3.ld.S121 __COHERENT_RAM_START__ = .; define
165 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
/tf-a-ffa_el3_spmc/bl32/sp_min/
A Dsp_min.ld.S115 __COHERENT_RAM_START__ = .; define
134 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
/tf-a-ffa_el3_spmc/bl2/aarch64/
A Dbl2_entrypoint.S83 adrp x0, __COHERENT_RAM_START__
84 add x0, x0, :lo12:__COHERENT_RAM_START__
/tf-a-ffa_el3_spmc/bl1/
A Dbl1.ld.S114 __COHERENT_RAM_START__ = .; define
145 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
/tf-a-ffa_el3_spmc/bl2u/
A Dbl2u.ld.S95 __COHERENT_RAM_START__ = .; define
/tf-a-ffa_el3_spmc/include/common/
A Dbl_common.h61 #define __COHERENT_RAM_START__ Load$$LR$$LR_COHERENT_RAM$$Base macro
151 IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE);
/tf-a-ffa_el3_spmc/bl2/aarch32/
A Dbl2_entrypoint.S88 ldr r0, =__COHERENT_RAM_START__
/tf-a-ffa_el3_spmc/include/arch/aarch64/
A Del3_common_macros.S421 adrp x0, __COHERENT_RAM_START__
422 add x0, x0, :lo12:__COHERENT_RAM_START__
/tf-a-ffa_el3_spmc/bl32/tsp/aarch64/
A Dtsp_entrypoint.S125 adrp x0, __COHERENT_RAM_START__
126 add x0, x0, :lo12:__COHERENT_RAM_START__
/tf-a-ffa_el3_spmc/bl31/
A Dbl31.ld.S154 __COHERENT_RAM_START__ = .; define
/tf-a-ffa_el3_spmc/include/arch/aarch32/
A Del3_common_macros.S378 ldr r0, =__COHERENT_RAM_START__
/tf-a-ffa_el3_spmc/docs/design/
A Dfirmware-design.rst1603 - ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.

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