| /tf-a-ffa_el3_spmc/services/std_svc/spm/spm_mm/ |
| A D | spm_mm_xlat.c | 35 unsigned int access = (attributes & SP_MEMORY_ATTRIBUTES_ACCESS_MASK) in smc_attr_to_mmap_attr() local
38 if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RW) { in smc_attr_to_mmap_attr()
40 } else if (access == SP_MEMORY_ATTRIBUTES_ACCESS_RO) { in smc_attr_to_mmap_attr()
44 assert(access == SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS); in smc_attr_to_mmap_attr()
|
| /tf-a-ffa_el3_spmc/include/lib/extensions/ |
| A D | ras.h | 45 .access = ERR_ACCESS_SYSREG, \
54 .access = ERR_ACCESS_MEMMAP, \
157 unsigned int access:1; member
|
| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | alt-boot-flows.rst | 8 the highest exception level is required. It allows full, direct access to the
27 configured to permit secure access only. This gives full access to the whole
35 - Little-endian data access;
|
| A D | firmware-design.rst | 15 hotplug and idle). Normal world software can access TF-A runtime services via
285 system register access to implemented trace registers.
287 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
304 - Enable the MMU and map the memory it needs to access.
372 access to Floating Point and Advanced SIMD registers by setting the
387 - Enable the MMU and map the memory it needs to access.
567 - Enable the MMU and map the memory it needs to access.
633 EL3, little-endian data access, and all interrupt sources masked:
753 EL3, little-endian data access, and all interrupt sources masked:
815 data access and all interrupt sources masked:
[all …]
|
| A D | reset-design.rst | 58 Therefore, the cold boot code has to arbitrate access to hardware resources
|
| /tf-a-ffa_el3_spmc/tools/fiptool/ |
| A D | win_posix.h | 126 inline int access(const char *path, int mode) in access() function
|
| A D | fiptool.c | 859 if (access(argv[0], F_OK) == 0) in update_cmd()
1000 if (access(file, F_OK) != 0 || fflag) { in unpack_cmd()
1114 if (outfile[0] != '\0' && access(outfile, F_OK) == 0 && !fflag) in remove_cmd()
|
| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | secure-partition-manager-mm.rst | 413 instruction access permissions.
419 instruction access permissions.
422 instruction access permissions.
668 - Bits[1:0] : Data access permission
670 - b'00 : No access
671 - b'01 : Read-Write access
673 - b'11 : Read-only access
743 - Bits[1:0] : Data access permission
745 - b'00 : No access
746 - b'01 : Read-Write access
[all …]
|
| A D | debugfs-design.rst | 73 - This permits direct access to a firmware driver, mainly for test purposes
103 - On concurrent access, a spinlock is implemented in the BL31 service to protect
|
| A D | ffa-manifest-binding.rst | 242 - exclusive-access
245 access and ownership of this device's MMIO region.
|
| A D | secure-partition-manager.rst | 524 translation regime, an SP can access its own manifest DTB blob and extract its
743 - Stage-2 translations for the NS IPA space access the NS PA space.
820 - Protection: An I/O device can be prohibited from read, write access to a
902 exclusive-access;
|
| /tf-a-ffa_el3_spmc/docs/plat/arm/tc/ |
| A D | index.rst | 9 loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
27 FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2
|
| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/include/t186/ |
| A D | tegra_mc_def.h | 334 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ argument
341 .override_enable = OVERRIDE_ ## access \
|
| /tf-a-ffa_el3_spmc/docs/threat_model/ |
| A D | threat_model.rst | 55 | ``DF3`` | | Debug and trace IP on a platform can allow access |
125 | ``AppDebug`` | | Physical attacker using debug signals to access |
128 | ``PhysicalAccess``| | Physical attacker having access to external device |
225 that require physical access are unlikely in server environments while
242 | | storage. It is possible for an attacker to access|
358 | ``Threat`` | | **An attacker with physical access can execute |
498 | | | Secure and non-secure clients access TF-A services |
679 | | access sensitive data or execute arbitrary |
684 | | normal world to access sensitive data or even |
711 | | access permissions. Memory configurations are |
[all …]
|
| A D | threat_model_spm.rst | 87 | ``DF7`` | External memory access. |
137 - Hardware attacks (non-invasive) requiring a physical access to the device,
382 | | getting access or gaining permissions to a memory |
577 | | access this service.** |
|
| /tf-a-ffa_el3_spmc/docs/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst | 14 - **0x2** = SPI direct access
|
| /tf-a-ffa_el3_spmc/docs/security_advisories/ |
| A D | security-advisory-tfv-3.rst | 29 contains flags to control data access permissions (``MT_RO``/``MT_RW``) and
47 permissions separately to data access permissions. All RO normal memory regions
|
| A D | security-advisory-tfv-6.rst | 132 cannot be used to access secure memory from the non-secure world, and is not
|
| /tf-a-ffa_el3_spmc/docs/plat/arm/ |
| A D | arm-build-options.rst | 13 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
17 kernel). Default is true (access to the frame is allowed).
40 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
|
| /tf-a-ffa_el3_spmc/docs/plat/ |
| A D | rz-g2.rst | 82 behind using direct shared memory access to BOOT_KIND_BASE _and_
162 - Boot the board in Mini-monitor mode and enable access to the
|
| A D | rcar-gen3.rst | 87 behind using direct shared memory access to BOOT_KIND_BASE _and_
189 - Boot the board in Mini-monitor mode and enable access to the
|
| A D | rpi4.rst | 62 This part knows how to access the MMC controller and how to parse a FAT
|
| /tf-a-ffa_el3_spmc/plat/arm/board/sgi575/fdts/ |
| A D | sgi575_stmm_config.dts | 86 * System registers region for access from S-EL0.
|
| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | security-hardening.rst | 42 Since the Non-secure world has access to the ``PMCR`` register, it can
|
| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 406 - Allow access to TZC controller on all chips
408 - Allow access to nor2 flash and system registers from S-EL0
947 - Disabled non-secure access to PRCM power control registers
1391 - intel: Enable bridge access, SiP SMC secure register access, and uboot
2731 - Clean up the usage of void pointers to access symbols
3035 software to access SVE functionality but disable access to SVE, SIMD and
3058 include specifying Non-privileged access.
3065 an attempt to access addresses in the higher VA range.
3165 the MT field in MPDIR and access the bit fields accordingly.
3406 access the bit fields accordingly.
[all …]
|