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Searched refs:addr (Results 1 – 25 of 163) sorted by relevance

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/tf-a-ffa_el3_spmc/include/lib/
A Dmmio.h14 *(volatile uint8_t*)addr = value; in mmio_write_8()
19 return *(volatile uint8_t*)addr; in mmio_read_8()
24 *(volatile uint16_t*)addr = value; in mmio_write_16()
29 return *(volatile uint16_t*)addr; in mmio_read_16()
36 mmio_write_16(addr, (mmio_read_16(addr) & ~clear) | set); in mmio_clrsetbits_16()
41 *(volatile uint32_t*)addr = value; in mmio_write_32()
46 return *(volatile uint32_t*)addr; in mmio_read_32()
56 return *(volatile uint64_t*)addr; in mmio_read_64()
61 mmio_write_32(addr, mmio_read_32(addr) & ~clear); in mmio_clrbits_32()
66 mmio_write_32(addr, mmio_read_32(addr) | set); in mmio_setbits_32()
[all …]
/tf-a-ffa_el3_spmc/common/backtrace/
A Dbacktrace.c66 xpaci(addr); in is_address_readable()
69 ats1e3r(addr); in is_address_readable()
71 ats1e2r(addr); in is_address_readable()
73 AT(ats1e1r, addr); in is_address_readable()
90 write_ats1cpr(addr); in is_address_readable()
92 write_ats1hr(addr); in is_address_readable()
94 write_ats1cpr(addr); in is_address_readable()
115 if (addr == 0U) in is_valid_object()
119 if ((addr + size) < addr) in is_valid_object()
141 if (addr == 0U) in is_valid_jump_address()
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/tf-a-ffa_el3_spmc/plat/marvell/armada/common/mss/
A Dmss_ipc_drv.c54 unsigned int addr; in mv_pm_ipc_queue_addr_get() local
61 addr = (unsigned int)(mv_pm_ipc_msg_base + in mv_pm_ipc_queue_addr_get()
66 return addr; in mv_pm_ipc_queue_addr_get()
77 unsigned int addr = mv_pm_ipc_queue_addr_get(); in mv_pm_ipc_msg_rx() local
79 msg->msg_reply = mmio_read_32(addr + IPC_MSG_REPLY_LOC); in mv_pm_ipc_msg_rx()
93 unsigned int addr = mv_pm_ipc_queue_addr_get(); in mv_pm_ipc_msg_tx() local
101 mmio_write_32(addr + IPC_MSG_SYNC_ID_LOC, msg_sync); in mv_pm_ipc_msg_tx()
102 mmio_write_32(addr + IPC_MSG_ID_LOC, msg_id); in mv_pm_ipc_msg_tx()
103 mmio_write_32(addr + IPC_MSG_CPU_ID_LOC, channel_id); in mv_pm_ipc_msg_tx()
104 mmio_write_32(addr + IPC_MSG_POWER_STATE_LOC, in mv_pm_ipc_msg_tx()
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/tf-a-ffa_el3_spmc/include/drivers/arm/css/
A Dcss_mhu_doorbell.h26 #define MHU_RING_DOORBELL(addr, modify_mask, preserve_mask) do { \ argument
27 uint32_t db = mmio_read_32(addr) & (preserve_mask); \
28 mmio_write_32(addr, db | (modify_mask)); \
31 #define MHU_V2_ACCESS_REQUEST(addr) \ argument
32 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
34 #define MHU_V2_CLEAR_REQUEST(addr) \ argument
35 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
37 #define MHU_V2_IS_ACCESS_READY(addr) \ argument
38 (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
/tf-a-ffa_el3_spmc/include/drivers/nxp/crypto/caam/
A Dcaam_io.h28 #define sec_in64(addr) ( \ argument
29 ((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \
30 (sec_in32(((uintptr_t)(addr)) + 4)))
31 #define sec_out64(addr, val) ({ \ argument
32 sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \
33 sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); })
37 #define sec_in64(addr) ( \ argument
38 ((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \
39 (sec_in32((uintptr_t)(addr))))
40 #define sec_out64(addr, val) ({ \ argument
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/tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/m0/include/
A Drk3399_mcu.h18 #define mmio_clrbits_32(addr, clear) \ argument
19 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)))
20 #define mmio_setbits_32(addr, set) \ argument
21 mmio_write_32(addr, (mmio_read_32(addr)) | (set))
22 #define mmio_clrsetbits_32(addr, clear, set) \ argument
23 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
/tf-a-ffa_el3_spmc/drivers/marvell/secure_dfx_access/
A Dmisc_dfx.c57 static _Bool is_valid(u_register_t addr) in is_valid() argument
59 switch (addr) { in is_valid()
85 if (!is_valid(addr)) in armada_dfx_sread()
88 *read = mmio_read_32(addr); in armada_dfx_sread()
93 static int armada_dfx_swrite(u_register_t addr, u_register_t val) in armada_dfx_swrite() argument
95 if (!is_valid(addr)) in armada_dfx_swrite()
98 mmio_write_32(addr, val); in armada_dfx_swrite()
104 u_register_t addr, u_register_t val) in mvebu_dfx_misc_handle() argument
108 debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val); in mvebu_dfx_misc_handle()
112 return armada_dfx_sread(read, addr); in mvebu_dfx_misc_handle()
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/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/driver/
A Dswreg.c169 sw_reg_name[reg_id-1], addr); in write_swreg_config()
186 sw_reg_name[reg_id-1], addr); in read_swreg_config()
227 int addr; in dump_swreg_firmware() local
232 for (addr = MIN_REG_ADDR; addr <= MAX_REG_ADDR; addr++) { in dump_swreg_firmware()
236 INFO("\t0x%x: 0x%04x\n", addr, data); in dump_swreg_firmware()
304 int addr; in swreg_firmware_update() local
310 for (addr = MAX_REG_ADDR; addr >= MIN_REG_ADDR; addr--) { in swreg_firmware_update()
312 FM_DATA[reg_id - 1][addr]); in swreg_firmware_update()
344 for (addr = MIN_REG_ADDR; addr <= MAX_REG_ADDR; addr++) { in swreg_firmware_update()
349 sw_reg_name[reg_id - 1], addr); in swreg_firmware_update()
[all …]
/tf-a-ffa_el3_spmc/drivers/renesas/rcar/cpld/
A Dulcb_cpld.c38 reg = mmio_read_32(addr); in gpio_set_value()
43 mmio_write_32(addr, reg); in gpio_set_value()
46 static void gpio_direction_output(uint32_t addr, uint8_t gpio) in gpio_direction_output() argument
50 reg = mmio_read_32(addr); in gpio_direction_output()
52 mmio_write_32(addr, reg); in gpio_direction_output()
55 static void gpio_pfc(uint32_t addr, uint8_t gpio) in gpio_pfc() argument
59 reg = mmio_read_32(addr); in gpio_pfc()
62 mmio_write_32(addr, reg); in gpio_pfc()
65 static void cpld_write(uint8_t addr, uint32_t data) in cpld_write() argument
79 gpio_set_value(GPIO_OUTDT6, MOSI, addr & 0x80); in cpld_write()
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/tf-a-ffa_el3_spmc/plat/qti/common/src/
A Dspmi_arb.c35 static int addr_to_apid(uint32_t addr) in addr_to_apid() argument
41 if ((reg != 0U) && ((addr & PPID_MASK) == (reg & PPID_MASK))) { in addr_to_apid()
73 (addr & 0xff) << 4 | (bytes - 1)); in arb_command()
76 int spmi_arb_read8(uint32_t addr) in spmi_arb_read8() argument
78 int apid = addr_to_apid(addr); in spmi_arb_read8()
84 arb_command(apid, OPC_EXT_READL, addr, 1); in spmi_arb_read8()
88 ERROR("SPMI_ARB read error [0x%x]: 0x%x\n", addr, ret); in spmi_arb_read8()
95 int spmi_arb_write8(uint32_t addr, uint8_t data) in spmi_arb_write8() argument
97 int apid = addr_to_apid(addr); in spmi_arb_write8()
104 arb_command(apid, OPC_EXT_WRITEL, addr, 1); in spmi_arb_write8()
[all …]
/tf-a-ffa_el3_spmc/include/drivers/brcm/
A Dchimp.h45 void bcm_chimp_write(uintptr_t addr, uint32_t value);
46 uint32_t bcm_chimp_read(uintptr_t addr);
48 void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits);
49 void bcm_chimp_setbits(uintptr_t addr, uint32_t bits);
57 static inline void bcm_chimp_write(uintptr_t addr, uint32_t value) in bcm_chimp_write() argument
60 static inline uint32_t bcm_chimp_read(uintptr_t addr) in bcm_chimp_read() argument
68 static inline void bcm_chimp_clrbits(uintptr_t addr, uint32_t bits) in bcm_chimp_clrbits() argument
71 static inline void bcm_chimp_setbits(uintptr_t addr, uint32_t bits) in bcm_chimp_setbits() argument
/tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/ptp3/
A Dmtk_ptp3_main.c33 unsigned int i, addr, value; in ptp3_init() local
45 addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + in ptp3_init()
49 ptp3_write(addr, value); in ptp3_init()
53 addr = ptp3_cfg2[i][PTP3_CFG_ADDR] + in ptp3_init()
61 ptp3_write(addr, value); in ptp3_init()
69 ptp3_write(addr, value & PTP3_CFG3_MASK1); in ptp3_init()
70 ptp3_write(addr, value & PTP3_CFG3_MASK2); in ptp3_init()
71 ptp3_write(addr, value & PTP3_CFG3_MASK3); in ptp3_init()
76 ptp3_write(addr, value & PTP3_CFG3_MASK1); in ptp3_init()
77 ptp3_write(addr, value & PTP3_CFG3_MASK2); in ptp3_init()
[all …]
/tf-a-ffa_el3_spmc/plat/nxp/common/setup/
A Dls_common.c67 (void *) info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
68 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
72 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
80 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
82 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
89 (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
100 (void *) info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
105 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
125 info_dram_regions->region[i].addr, in mmap_add_ddr_region_dynamically()
142 (info_dram_regions->region[i].addr in mmap_add_ddr_region_dynamically()
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/tf-a-ffa_el3_spmc/plat/arm/board/corstone700/common/drivers/mhu/
A Dmhu.h21 #define MHU_V2_ACCESS_REQUEST(addr) \ argument
22 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x1)
24 #define MHU_V2_CLEAR_REQUEST(addr) \ argument
25 mmio_write_32((addr) + MHU_V2_ACCESS_REQ_OFFSET, 0x0)
27 #define MHU_V2_IS_ACCESS_READY(addr) \ argument
28 (mmio_read_32((addr) + MHU_V2_ACCESS_READY_OFFSET) & 0x1)
/tf-a-ffa_el3_spmc/drivers/marvell/comphy/
A Dphy-comphy-common.h134 data = mmio_read_16(addr) & mask; in polling_with_timeout()
136 data = mmio_read_32(addr) & mask; in polling_with_timeout()
148 addr, data, mask); in reg_set()
149 debug("old value = 0x%x ==> ", mmio_read_32(addr)); in reg_set()
150 mmio_clrsetbits_32(addr, mask, data); in reg_set()
152 debug("new val 0x%x\n", mmio_read_32(addr)); in reg_set()
155 static inline void __unused reg_set16(uintptr_t addr, uint16_t data, in reg_set16() argument
160 addr, data, mask); in reg_set16()
161 debug("old value = 0x%x ==> ", mmio_read_16(addr)); in reg_set16()
162 mmio_clrsetbits_16(addr, mask, data); in reg_set16()
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/tf-a-ffa_el3_spmc/drivers/brcm/
A Dchimp.c19 #define CHIMP_PREPARE_ACCESS_WINDOW(addr) \ argument
23 addr & 0xffc00000)\
25 #define CHIMP_INDIRECT_TGT_ADDR(addr) \ argument
37 void bcm_chimp_write(uintptr_t addr, uint32_t value) in bcm_chimp_write() argument
39 CHIMP_PREPARE_ACCESS_WINDOW(addr); in bcm_chimp_write()
43 uint32_t bcm_chimp_read(uintptr_t addr) in bcm_chimp_read() argument
45 CHIMP_PREPARE_ACCESS_WINDOW(addr); in bcm_chimp_read()
46 return mmio_read_32(CHIMP_INDIRECT_TGT_ADDR(addr)); in bcm_chimp_read()
51 CHIMP_PREPARE_ACCESS_WINDOW(addr); in bcm_chimp_clrbits()
57 CHIMP_PREPARE_ACCESS_WINDOW(addr); in bcm_chimp_setbits()
[all …]
/tf-a-ffa_el3_spmc/plat/imx/common/
A Dimx_clock.c19 uintptr_t addr; in imx_clock_target_set() local
24 addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root; in imx_clock_target_set()
25 mmio_write_32(addr, val); in imx_clock_target_set()
31 uintptr_t addr; in imx_clock_target_clr() local
36 addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root_clr; in imx_clock_target_clr()
37 mmio_write_32(addr, val); in imx_clock_target_clr()
43 uintptr_t addr; in imx_clock_gate_enable() local
50 addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_set; in imx_clock_gate_enable()
52 addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_clr; in imx_clock_gate_enable()
54 mmio_write_32(addr, CCM_CCGR_SETTING0_DOM_CLK_ALWAYS); in imx_clock_gate_enable()
A Dimx_aips.c16 uintptr_t addr; in imx_aips_set_default_access() local
27 addr = (uintptr_t)&aips_regs->aipstz_mpr; in imx_aips_set_default_access()
28 mmio_write_32(addr, 0x77777777); in imx_aips_set_default_access()
41 addr = (uintptr_t)&aips_regs->aipstz_opacr[i]; in imx_aips_set_default_access()
42 mmio_write_32(addr, 0x00000000); in imx_aips_set_default_access()
A Dimx_snvs.c15 uintptr_t addr; in imx_snvs_init() local
18 addr = (uintptr_t)&snvs->hpcomr; in imx_snvs_init()
19 val = mmio_read_32(addr); in imx_snvs_init()
21 mmio_write_32(addr, val); in imx_snvs_init()
A Dimx_io_mux.c14 uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_mux_offset); in imx_io_muxc_set_pad_alt_function() local
16 mmio_write_32(addr, alt_function); in imx_io_muxc_set_pad_alt_function()
21 uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_feature_offset); in imx_io_muxc_set_pad_features() local
23 mmio_write_32(addr, pad_features); in imx_io_muxc_set_pad_features()
/tf-a-ffa_el3_spmc/drivers/marvell/
A Dcache_llc.c160 uintptr_t addr, end_addr; in llc_sram_test() local
167 for (addr = PLAT_MARVELL_TRUSTED_RAM_BASE, in llc_sram_test()
169 addr < end_addr; addr += 4) { in llc_sram_test()
170 mmio_write_32(addr, addr); in llc_sram_test()
174 for (addr = PLAT_MARVELL_TRUSTED_RAM_BASE, in llc_sram_test()
176 addr < end_addr; addr += 4) { in llc_sram_test()
177 data = mmio_read_32(addr); in llc_sram_test()
178 if (data != addr) { in llc_sram_test()
180 msg, addr); in llc_sram_test()
/tf-a-ffa_el3_spmc/drivers/rpi3/mailbox/
A Drpi3_mbox.c25 uintptr_t resp_addr, addr; in rpi3_vc_mailbox_request_send() local
29 addr = (uintptr_t)req; in rpi3_vc_mailbox_request_send()
32 flush_dcache_range(addr, req_size); in rpi3_vc_mailbox_request_send()
50 RPI3_CHANNEL_ARM_TO_VC | (uint32_t) addr); in rpi3_vc_mailbox_request_send()
75 if (addr != resp_addr) { in rpi3_vc_mailbox_request_send()
81 inv_dcache_range(addr, req_size); in rpi3_vc_mailbox_request_send()
/tf-a-ffa_el3_spmc/plat/hisilicon/hikey960/
A Dhikey960_mcu_load.c19 #define ADDR_CONVERT(addr) ((addr) < 0x40000 ? \ argument
20 (addr) + 0xFFF30000 : \
21 (addr) + 0x40000000)
/tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/ptp3/
A Dmtk_ptp3_common.h16 #define ptp3_read(addr) mmio_read_32((uintptr_t)addr) argument
17 #define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val) argument
/tf-a-ffa_el3_spmc/drivers/nxp/ddr/phy-gen2/
A Dphy.c640 uint32_t addr; in prog_cal_rate_run() local
656 uint32_t addr; in prog_seq0bdly0() local
1008 uint32_t addr; in prog_tx_pre_drv_mode() local
1035 uint32_t addr; in prog_atx_pre_drv_mode() local
1153 uint32_t addr; in prog_pll_ctrl() local
1220 uint32_t addr; in prog_pll_pwr_dn() local
1367 uint32_t addr; in prog_tx_odt_drv_stren() local
1442 uint32_t addr; in prog_tx_impedance_ctrl1() local
1541 uint32_t addr; in prog_atx_impedance() local
1566 uint32_t addr; in prog_dfi_mode() local
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