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Searched refs:ap_index (Results 1 – 18 of 18) sorted by relevance

/tf-a-ffa_el3_spmc/drivers/marvell/
A Dcache_llc.c21 #define CCU_HTC_CR(ap_index) (MVEBU_CCU_BASE(ap_index) + 0x200) argument
35 llc_cache_sync(ap_index); in llc_flush_all()
41 llc_cache_sync(ap_index); in llc_clean_all()
44 void llc_inv_all(int ap_index) in llc_inv_all() argument
47 llc_cache_sync(ap_index); in llc_inv_all()
52 llc_flush_all(ap_index); in llc_disable()
62 llc_inv_all(ap_index); in llc_enable()
103 llc_enable(ap_index, 1); in llc_runtime_enable()
122 llc_enable(ap_index, 1); in llc_sram_enable()
123 llc_inv_all(ap_index); in llc_sram_enable()
[all …]
A Dccu.c67 static void dump_ccu(int ap_index) in dump_ccu() argument
81 alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, in dump_ccu()
173 ccu_enable_win(ap_index, win, win_id); in ccu_temp_win_insert()
204 ccu_disable_win(ap_index, win_id); in ccu_temp_win_remove()
266 ccu_disable_win(ap_index, win_id); in ccu_dram_win_config()
271 ccu_enable_win(ap_index, win, win_id); in ccu_dram_win_config()
314 int init_ccu(int ap_index) in init_ccu() argument
347 dram_target = ccu_dram_target_get(ap_index); in init_ccu()
368 ccu_disable_win(ap_index, win_id); in init_ccu()
381 ccu_enable_win(ap_index, win, win_id); in init_ccu()
[all …]
A Dgwin.c82 mmio_write_32(GWIN_ALR_OFFSET(ap_index, win_num), alr); in gwin_enable_window()
86 mmio_write_32(GWIN_CR_OFFSET(ap_index, win_num), in gwin_enable_window()
114 gwin_enable_window(ap_index, win, win_id); in gwin_temp_win_insert()
146 gwin_disable_window(ap_index, win_id); in gwin_temp_win_remove()
152 static void dump_gwin(int ap_index) in dump_gwin() argument
177 int init_gwin(int ap_index) in init_gwin() argument
201 gwin_disable_window(ap_index, win_id); in init_gwin()
206 gwin_enable_window(ap_index, win, win_id); in init_gwin()
217 win_reg = mmio_read_32(CCU_GRU_CR_OFFSET(ap_index)); in init_gwin()
219 mmio_write_32(CCU_GRU_CR_OFFSET(ap_index), win_reg); in init_gwin()
[all …]
A Dio_win.c83 mmio_write_32(IO_WIN_ALR_OFFSET(ap_index, win_num), alr); in io_win_enable_window()
119 io_win_enable_window(ap_index, win, win_id); in iow_temp_win_insert()
149 io_win_disable_window(ap_index, win_id); in iow_temp_win_remove()
155 static void dump_io_win(int ap_index) in dump_io_win() argument
169 trgt_id = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, in dump_io_win()
178 mmio_read_32(MVEBU_IO_WIN_BASE(ap_index) + in dump_io_win()
225 int init_io_win(int ap_index) in init_io_win() argument
245 win_reg = marvell_get_io_win_gcr_target(ap_index); in init_io_win()
251 io_win_disable_window(ap_index, win_id); in init_io_win()
258 io_win_enable_window(ap_index, win, win_id); in init_io_win()
[all …]
/tf-a-ffa_el3_spmc/include/drivers/marvell/
A Dcache_llc.h47 void llc_cache_sync(int ap_index);
48 void llc_flush_all(int ap_index);
49 void llc_clean_all(int ap_index);
50 void llc_inv_all(int ap_index);
51 void llc_disable(int ap_index);
52 void llc_enable(int ap_index, int excl_mode);
53 int llc_is_exclusive(int ap_index);
54 void llc_runtime_enable(int ap_index);
56 int llc_sram_enable(int ap_index, int size);
57 void llc_sram_disable(int ap_index);
[all …]
A Dccu.h42 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
43 void ccu_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
44 void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
45 void ccu_dram_win_config(int ap_index, struct addr_map_win *win);
46 void ccu_dram_target_set(int ap_index, uint32_t target);
49 int ccu_is_win_enabled(int ap_index, uint32_t win_id);
A Dgwin.h15 int init_gwin(int ap_index);
16 void gwin_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
17 void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
A Dio_win.h15 int init_io_win(int ap_index);
16 void iow_temp_win_insert(int ap_index, struct addr_map_win *win, int size);
17 void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size);
/tf-a-ffa_el3_spmc/drivers/marvell/mc_trustzone/
A Dmc_trustzone.c29 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id) in tz_enable_win() argument
61 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), val); in tz_enable_win()
64 MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), in tz_enable_win()
65 mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id))); in tz_enable_win()
67 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), in tz_enable_win()
71 MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), in tz_enable_win()
72 mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id))); in tz_enable_win()
A Dmc_trustzone.h25 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id);
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a70x0/board/
A Dmarvell_plat_config.c52 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
57 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
122 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a70x0_amc/board/
A Dmarvell_plat_config.c49 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
54 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
113 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/tf-a-ffa_el3_spmc/plat/marvell/octeontx/otx2/t91/t9130/board/
A Dmarvell_plat_config.c70 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
79 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
173 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0_mcbin/board/
A Dmarvell_plat_config.c90 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
95 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
181 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0_puzzle/board/
A Dmarvell_plat_config.c94 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
99 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
182 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/tf-a-ffa_el3_spmc/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/
A Dmarvell_plat_config.c93 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
102 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument
205 int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_ccu_memory_map() argument
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/include/
A Da8k_plat_def.h36 #define MVEBU_IO_WIN_BASE(ap_index) (MVEBU_RFU_BASE) argument
43 #define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000) argument
46 #define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000) argument
/tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0/board/
A Dmarvell_plat_config.c60 uint32_t marvell_get_io_win_gcr_target(int ap_index) in marvell_get_io_win_gcr_target() argument
65 int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, in marvell_get_io_win_memory_map() argument

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