| /tf-a-ffa_el3_spmc/plat/arm/board/juno/ |
| A D | juno_bl31_setup.c | 16 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
20 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2()
23 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2()
27 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2()
30 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/services/arm_arch_svc/ |
| A D | arm_arch_svc_setup.c | 22 static int32_t smccc_arch_features(u_register_t arg1) in smccc_arch_features() argument
24 switch (arg1) { in smccc_arch_features()
29 return plat_is_smccc_feature_available(arg1); in smccc_arch_features()
86 static int32_t smccc_arch_id(u_register_t arg1) in smccc_arch_id() argument
88 if (arg1 == SMCCC_GET_SOC_REVISION) { in smccc_arch_id()
91 if (arg1 == SMCCC_GET_SOC_VERSION) { in smccc_arch_id()
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/ |
| A D | fvp_bl31_setup.c | 21 u_register_t arg1, u_register_t arg2, u_register_t arg3) in bl31_early_platform_setup2() argument
26 INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1); in bl31_early_platform_setup2()
28 fconf_populate("FW_CONFIG", arg1); in bl31_early_platform_setup2()
32 arg1 = soc_fw_config_info->config_addr; in bl31_early_platform_setup2()
36 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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| A D | fvp_bl2_setup.c | 24 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
26 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
71 ep_info->args.arg1 = (uint32_t)fw_config_base; in plat_get_next_bl_params()
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| /tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/pm_service/ |
| A D | pm_api_ioctl.c | 616 unsigned int arg1, in pm_api_ioctl() argument
627 ret = pm_ioctl_set_rpu_oper_mode(arg1); in pm_api_ioctl()
630 ret = pm_ioctl_config_boot_addr(nid, arg1); in pm_api_ioctl()
633 ret = pm_ioctl_config_tcm_comb(arg1); in pm_api_ioctl()
639 ret = pm_ioctl_set_sgmii_mode(nid, arg1); in pm_api_ioctl()
642 ret = pm_ioctl_sd_dll_reset(nid, arg1); in pm_api_ioctl()
660 ret = pm_ioctl_write_ggs(arg1, arg2); in pm_api_ioctl()
663 ret = pm_ioctl_read_ggs(arg1, value); in pm_api_ioctl()
666 ret = pm_ioctl_write_pggs(arg1, arg2); in pm_api_ioctl()
669 ret = pm_ioctl_read_pggs(arg1, value); in pm_api_ioctl()
[all …]
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/dfd/ |
| A D | plat_dfd.c | 112 uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1, in dfd_smc_dispatcher() argument
119 dfd_setup(arg1, arg2, arg3); in dfd_smc_dispatcher()
123 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
124 ret = mmio_read_32(MISC1_CFG_BASE + arg1); in dfd_smc_dispatcher()
129 if (arg1 <= 0x200) { in dfd_smc_dispatcher()
130 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
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| /tf-a-ffa_el3_spmc/bl2/ |
| A D | bl2_main.c | 36 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_setup() argument
40 bl2_early_platform_setup2(arg0, arg1, arg2, arg3); in bl2_setup()
58 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_el3_setup() argument
62 bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_el3_setup()
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| /tf-a-ffa_el3_spmc/bl32/tsp/ |
| A D | tsp_private.h | 67 uint64_t arg1,
75 uint64_t arg1,
84 uint64_t arg1,
115 uint64_t arg1, uint64_t arg2,
120 uint64_t arg1,
129 uint64_t arg1,
138 uint64_t arg1,
147 uint64_t arg1,
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| A D | tsp_main.c | 105 uint64_t arg1, in set_smc_args() argument
283 uint64_t arg1, in tsp_cpu_off_main() argument
350 uint64_t arg1, in tsp_cpu_suspend_main() argument
392 uint64_t arg1, in tsp_cpu_resume_main() argument
430 uint64_t arg1, in tsp_system_off_main() argument
462 uint64_t arg1, in tsp_system_reset_main() argument
526 results[0] = arg1; in tsp_smc_handler()
580 uint64_t arg1, in tsp_abort_smc_handler() argument
622 uint64_t arg1, in handle_framework_message() argument
747 uint64_t arg1, in ffa_test_relay() argument
[all …]
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| /tf-a-ffa_el3_spmc/drivers/arm/css/scmi/ |
| A D | scmi_private.h | 97 #define SCMI_PAYLOAD_ARG1(payld_arr, arg1) \ argument
98 mmio_write_32((uintptr_t)&payld_arr[0], arg1)
100 #define SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2) do { \ argument
101 SCMI_PAYLOAD_ARG1(payld_arr, arg1); \
105 #define SCMI_PAYLOAD_ARG3(payld_arr, arg1, arg2, arg3) do { \ argument
106 SCMI_PAYLOAD_ARG2(payld_arr, arg1, arg2); \
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| A D | mce.c | 175 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); in mce_command_handler()
189 (uint32_t)arg1, (uint32_t)arg2, (uint8_t)arg3, in mce_command_handler()
213 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); in mce_command_handler()
218 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
226 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
240 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); in mce_command_handler()
294 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); in mce_command_handler()
298 write_ctx_reg(gp_regs, CTX_GPREG_X2, (arg1)); in mce_command_handler()
304 ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1); in mce_command_handler()
335 write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1)); in mce_command_handler()
[all …]
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| /tf-a-ffa_el3_spmc/plat/arm/board/corstone700/sp_min/ |
| A D | corstone700_sp_min_setup.c | 9 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp_ve/sp_min/ |
| A D | fvp_ve_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /tf-a-ffa_el3_spmc/plat/arm/board/a5ds/ |
| A D | a5ds_bl2_setup.c | 9 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
12 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/layerscape/board/ls1043/ |
| A D | ls1043_bl2_setup.c | 12 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
15 ls_bl2_early_platform_setup((meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/arm/board/a5ds/sp_min/ |
| A D | a5ds_sp_min_setup.c | 11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /tf-a-ffa_el3_spmc/include/bl2/ |
| A D | bl2.h | 12 void bl2_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
14 void bl2_el3_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2,
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| /tf-a-ffa_el3_spmc/plat/arm/common/sp_min/ |
| A D | arm_sp_min_setup.c | 97 bl33_image_ep_info.args.arg1 = ~0U; in arm_sp_min_early_platform_setup()
136 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
139 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
158 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument
161 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp_ve/ |
| A D | fvp_ve_bl2_setup.c | 16 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
18 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/sp_min/ |
| A D | fvp_sp_min_setup.c | 18 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
21 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in plat_arm_sp_min_early_platform_setup()
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| /tf-a-ffa_el3_spmc/plat/arm/board/tc/ |
| A D | tc_bl31_setup.c | 41 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
44 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/qemu/common/ |
| A D | qemu_bl2_setup.c | 29 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
32 meminfo_t *mem_layout = (void *)arg1; in bl2_early_platform_setup2()
178 bl_mem_params->ep_info.args.arg1; in qemu_bl2_handle_post_image_load()
179 bl_mem_params->ep_info.args.arg1 = 0; in qemu_bl2_handle_post_image_load()
204 bl_mem_params->ep_info.args.arg1 = 0U; in qemu_bl2_handle_post_image_load()
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| /tf-a-ffa_el3_spmc/plat/rpi/rpi3/ |
| A D | rpi3_bl31_setup.c | 70 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
81 assert(arg1 == RPI3_BL31_PLAT_PARAM_VAL); in bl31_early_platform_setup2()
123 bl33_image_ep_info.args.arg1 = ~0U; in bl31_early_platform_setup2()
134 bl33_image_ep_info.args.arg1 = 0ULL; in bl31_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/arm/css/common/ |
| A D | css_bl2_setup.c | 56 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
59 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); in bl2_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/imx/imx7/common/ |
| A D | imx7_bl2_el3_common.c | 87 bl_mem_params->ep_info.args.arg1; in bl2_plat_handle_post_image_load()
88 bl_mem_params->ep_info.args.arg1 = 0; in bl2_plat_handle_post_image_load()
150 void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2, in bl2_el3_early_platform_setup() argument
166 imx7_platform_setup(arg1, arg2, arg3, arg4); in bl2_el3_early_platform_setup()
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