Searched refs:arg5 (Results 1 – 9 of 9) sorted by relevance
| /tf-a-ffa_el3_spmc/bl32/tsp/ |
| A D | tsp_private.h | 71 uint64_t arg5,
79 uint64_t arg5,
88 uint64_t arg5,
117 uint64_t arg5, uint64_t arg6);
124 uint64_t arg5,
133 uint64_t arg5,
142 uint64_t arg5,
151 uint64_t arg5,
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| A D | tsp_main.c | 109 uint64_t arg5, in set_smc_args() argument
287 uint64_t arg5, in tsp_cpu_off_main() argument
396 uint64_t arg5, in tsp_cpu_resume_main() argument
434 uint64_t arg5, in tsp_system_off_main() argument
466 uint64_t arg5, in tsp_system_reset_main() argument
584 uint64_t arg5, in tsp_abort_smc_handler() argument
626 uint64_t arg5, in handle_framework_message() argument
672 uint32_t arg5, in ffa_msg_send_direct_resp() argument
691 uint32_t arg5, in ffa_msg_send_direct_req() argument
751 uint64_t arg5, in ffa_test_relay() argument
[all …]
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| A D | mce.c | 162 uint64_t ret64 = 0, arg3, arg4, arg5; in mce_command_handler() local
186 arg5 = read_ctx_reg(gp_regs, CTX_GPREG_X6); in mce_command_handler()
190 (uint32_t)arg4, (uint8_t)arg5); in mce_command_handler()
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| /tf-a-ffa_el3_spmc/include/export/common/ |
| A D | ep_info_exp.h | 72 uint64_t arg5; member
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/common/ |
| A D | tegra_bl31_setup.c | 208 args->arg3 = bl32_args.arg5; in plat_trusty_set_boot_args()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt6795/ |
| A D | bl31_plat_setup.c | 229 bl33_image_ep_info.args.arg5 = pmtk_bl_param->bootarg_size; in bl31_early_platform_setup2()
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| /tf-a-ffa_el3_spmc/plat/xilinx/versal/pm_service/ |
| A D | pm_api_sys.c | 68 #define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
69 pl[5] = (uint32_t)(arg5); \
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| /tf-a-ffa_el3_spmc/plat/xilinx/zynqmp/pm_service/ |
| A D | pm_api_sys.c | 63 #define PM_PACK_PAYLOAD6(pl, arg0, arg1, arg2, arg3, arg4, arg5) { \ argument
64 pl[5] = (uint32_t)(arg5); \
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| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | coding-guidelines.rst | 435 u_register_t arg5;
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