| /tf-a-ffa_el3_spmc/services/std_svc/spm/spm_mm/ |
| A D | spm_mm_xlat.c | 31 static unsigned int smc_attr_to_mmap_attr(unsigned int attributes) in smc_attr_to_mmap_attr() argument
35 unsigned int access = (attributes & SP_MEMORY_ATTRIBUTES_ACCESS_MASK) in smc_attr_to_mmap_attr()
49 if ((attributes & SP_MEMORY_ATTRIBUTES_NON_EXEC) == 0) { in smc_attr_to_mmap_attr()
93 uint32_t attributes; in spm_memory_attributes_get_smc_handler() local
98 base_va, &attributes); in spm_memory_attributes_get_smc_handler()
106 return (int32_t) smc_mmap_to_smc_attr(attributes); in spm_memory_attributes_get_smc_handler()
119 uint32_t attributes = (uint32_t) smc_attributes; in spm_memory_attributes_set_smc_handler() local
123 INFO(" Attributes : 0x%x\n", attributes); in spm_memory_attributes_set_smc_handler()
129 smc_attr_to_mmap_attr(attributes)); in spm_memory_attributes_set_smc_handler()
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| /tf-a-ffa_el3_spmc/bl32/tsp/ |
| A D | ffa_helpers.c | 21 ffa_memory_attributes_t attributes, ffa_memory_region_flags_t flags, in ffa_memory_region_init_header() argument
26 memory_region->attributes = attributes; in ffa_memory_region_init_header()
55 ffa_memory_attributes_t attributes = 0; in ffa_memory_retrieve_request_init() local
62 ffa_set_memory_type_attr(&attributes, type); in ffa_memory_retrieve_request_init()
63 ffa_set_memory_cacheability_attr(&attributes, cacheability); in ffa_memory_retrieve_request_init()
64 ffa_set_memory_shareability_attr(&attributes, shareability); in ffa_memory_retrieve_request_init()
66 ffa_memory_region_init_header(memory_region, sender, attributes, flags, in ffa_memory_retrieve_request_init()
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| A D | ffa_helpers.h | 273 ffa_memory_attributes_t attributes; member
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| /tf-a-ffa_el3_spmc/drivers/scmi-msg/ |
| A D | power_domain.h | 31 uint32_t attributes; member
41 uint32_t attributes; member
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| A D | common.h | 50 uint32_t attributes; member
61 uint32_t attributes; member
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| A D | clock.h | 43 uint32_t attributes; member
103 uint32_t attributes; member
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| A D | power_domain.c | 90 return_values.attributes = plat_scmi_pd_count(msg->agent_id); in report_attributes()
107 .attributes = 0U, in report_message_attributes()
152 return_values.attributes = plat_scmi_pd_get_attributes(msg->agent_id, pd_id); in scmi_pd_attributes()
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| A D | reset_domain.h | 44 uint32_t attributes; member
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| A D | clock.c | 98 .attributes = SCMI_CLOCK_PROTOCOL_ATTRIBUTES(1U, agent_count), in report_attributes()
115 .attributes = 0U, in report_message_attributes()
161 return_values.attributes = plat_scmi_clock_get_state(msg->agent_id, in scmi_clock_attributes()
242 enable = in_args->attributes & SCMI_CLOCK_CONFIG_SET_ENABLE_MASK; in scmi_clock_config_set()
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| A D | base.c | 39 .attributes = SCMI_BASE_PROTOCOL_ATTRIBUTES(protocol_count, 0U), in report_attributes()
56 .attributes = 0U, in report_message_attributes()
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| A D | reset_domain.c | 67 .attributes = plat_scmi_rstd_count(msg->agent_id), in report_attributes()
84 .attributes = 0U, in report_message_attributes()
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| /tf-a-ffa_el3_spmc/lib/xlat_tables_v2/ |
| A D | xlat_tables_utils.c | 329 uintptr_t base_va, uint32_t *attributes, uint64_t **table_entry, in xlat_get_mem_attributes_internal() argument
379 assert(attributes != NULL); in xlat_get_mem_attributes_internal()
380 *attributes = 0U; in xlat_get_mem_attributes_internal()
385 *attributes |= MT_MEMORY; in xlat_get_mem_attributes_internal()
387 *attributes |= MT_NON_CACHEABLE; in xlat_get_mem_attributes_internal()
390 *attributes |= MT_DEVICE; in xlat_get_mem_attributes_internal()
396 *attributes |= MT_RW; in xlat_get_mem_attributes_internal()
402 *attributes |= MT_USER; in xlat_get_mem_attributes_internal()
408 *attributes |= MT_NS; in xlat_get_mem_attributes_internal()
413 *attributes |= MT_EXECUTE_NEVER; in xlat_get_mem_attributes_internal()
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| /tf-a-ffa_el3_spmc/plat/arm/board/fvp/fdts/ |
| A D | optee_sp_manifest.dts | 40 attributes = <0x3>; /* read-write */
46 attributes = <0x3>; /* read-write */
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| /tf-a-ffa_el3_spmc/docs/components/ |
| A D | secure-partition-manager-mm.rst | 412 1. Device regions are mapped with nGnRE attributes and Execute Never
426 attributes.
492 memory attributes described earlier.
564 memory attributes described earlier.
609 the Secure EL1&0 Translation regime with appropriate memory attributes.
611 attributes used in the Translation tables. The definitions of these attributes
636 attributes.
647 Request the permission attributes of a memory region from S-EL0.
660 attributes of the translation granule it lies in are returned.
720 Set the permission attributes of a memory region from S-EL0.
[all …]
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| A D | ffa-manifest-binding.rst | 167 - attributes [mandatory]
207 - attributes [mandatory]
230 - A list of (id, attributes) pair describing the device interrupts, where:
233 - attributes: A <u32> value,
234 containing the attributes for each interrupt ID:
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| A D | xlat-tables-lib-v2-design.rst | 26 #. Support for changing memory attributes of memory regions at run-time.
62 - its attributes;
71 The region attributes specify the type of memory (for example device or cached
74 the EL1&0 translation regime, the attributes also specify whether the region is
90 with different memory attributes, the library might need to split the existing
301 translation tables and helpers to query memory attributes and to modify them.
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| A D | sdei.rst | 57 available on the platform, along with their attributes.
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| A D | secure-partition-manager.rst | 296 An SP manifest describes SP attributes as defined in `[1]`_
898 attributes = <0x3>;
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/scat/ |
| A D | bl31.scat | 245 * memory attributes for the coherent data page tables.
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| /tf-a-ffa_el3_spmc/docs/security_advisories/ |
| A D | security-advisory-tfv-3.rst | 28 has memory attributes represented by the ``mmap_attr_t`` enumeration type. This
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| /tf-a-ffa_el3_spmc/docs/design/ |
| A D | psci-pd-tree.rst | 36 #. The attributes of a core power domain differ from the attributes of power
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| A D | firmware-design.rst | 708 uint32_t attr; /* attributes: unused bits SBZ */
1318 element of the array specifies the interrupt number and its attributes
1595 memory regions to set the right memory attributes. When
2013 shareability, cacheability and memory attributes is accessed by multiple CPUs
2023 mismatched attributes from various CPUs are allocated in a coherent memory
2028 due to mismatched memory attributes.
2033 work around the issue of mismatched memory attributes by performing software
2121 CPUs with mismatched memory attributes. Since these fields are a part of the
2142 into coherency issues associated with mismatched attributes.
2420 mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
[all …]
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| /tf-a-ffa_el3_spmc/docs/threat_model/ |
| A D | threat_model.rst | 710 | | and assign attributes including memory types and |
713 | | sure the correct attributes are assigned to |
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| /tf-a-ffa_el3_spmc/docs/process/ |
| A D | coding-style.rst | 252 Place any function attributes after the function type and before the function
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| /tf-a-ffa_el3_spmc/docs/ |
| A D | change-log.rst | 3053 - Introduced APIs to get and set the memory attributes of a region.
3057 translation regime, and extended the memory map region attributes to
3073 alignment needed between memory attributes and attributes specified in
3621 - Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to
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