Home
last modified time | relevance | path

Searched refs:bakery (Results 1 – 8 of 8) sorted by relevance

/tf-a-ffa_el3_spmc/lib/locks/bakery/
A Dbakery_lock_coherent.c50 assert(bakery_ticket_number(bakery->lock_data[me]) == 0U); in bakery_get_ticket()
65 their_ticket = bakery_ticket_number(bakery->lock_data[they]); in bakery_get_ticket()
92 void bakery_lock_get(bakery_lock_t *bakery) in bakery_lock_get() argument
100 assert_bakery_entry_valid(me, bakery); in bakery_lock_get()
103 my_ticket = bakery_get_ticket(bakery, me); in bakery_lock_get()
116 their_bakery_data = bakery->lock_data[they]; in bakery_lock_get()
135 bakery_ticket_number(bakery->lock_data[they])); in bakery_lock_get()
149 void bakery_lock_release(bakery_lock_t *bakery) in bakery_lock_release() argument
153 assert_bakery_entry_valid(me, bakery); in bakery_lock_release()
154 assert(bakery_ticket_number(bakery->lock_data[me]) != 0U); in bakery_lock_release()
[all …]
/tf-a-ffa_el3_spmc/include/lib/
A Dbakery_lock.h95 static inline void bakery_lock_init(bakery_lock_t *bakery) {} in bakery_lock_init() argument
96 void bakery_lock_get(bakery_lock_t *bakery);
97 void bakery_lock_release(bakery_lock_t *bakery);
/tf-a-ffa_el3_spmc/lib/psci/
A Dpsci_lib.mk28 PSCI_LIB_SOURCES += lib/locks/bakery/bakery_lock_coherent.c
30 PSCI_LIB_SOURCES += lib/locks/bakery/bakery_lock_normal.c
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/scat/
A Dbl31.scat178 * The compiler will allocate enough memory for one CPU's bakery locks,
193 /* padded memory section to store per cpu bakery locks */
197 /* PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements */
/tf-a-ffa_el3_spmc/docs/design/
A Dfirmware-design.rst2109 * choosing its bakery number.
2110 * Bits[1 - 15] : number. This is the bakery number allocated.
2144 The bakery lock data structure ``bakery_info_t`` is defined for use when
2153 * choosing its bakery number.
2154 * Bits[1 - 15] : number. This is the bakery number allocated.
2161 system represents the complete bakery lock. The view in memory for a system
2162 with n bakery locks are:
2201 Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
2217 There is however a performance impact for bakery locks, due to:
2220 - Multiple cache line reads for each lock operation, since the bakery locks
[all …]
/tf-a-ffa_el3_spmc/docs/getting_started/
A Dpsci-lib-integration-guide.rst300 functions like bakery locks and spin locks are also included in the library.
A Dporting-guide.rst1971 accommodate all the bakery locks.
1978 accessing per-cpu bakery lock information.
/tf-a-ffa_el3_spmc/docs/
A Dchange-log.rst1325 - locks: bakery: Use is_dcache_enabled() helper and add a DMB to
1683 - locks: T589: Fix insufficient ordering guarantees in bakery lock
2465 - Optimized bakery locks when hardware-assisted coherency is enabled using the
3246 - Use spin-locks instead of bakery locks.
3784 - The bakery lock structure for coherent memory has been optimised.
4096 - Removed calling CPU mpidr from the bakery lock API, saving 160 bytes.

Completed in 25 milliseconds