Searched refs:clr_mask (Results 1 – 5 of 5) sorted by relevance
| /tf-a-ffa_el3_spmc/include/drivers/allwinner/ |
| A D | axp.h | 44 int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask);
45 #define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) argument
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| /tf-a-ffa_el3_spmc/drivers/allwinner/axp/ |
| A D | common.c | 31 int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) in axp_clrsetbits() argument
40 val = (ret & ~clr_mask) | set_mask; in axp_clrsetbits()
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| /tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/ |
| A D | bl31_setup.c | 495 unsigned int clr_mask = SCR_AXCACHE_CONFIG_MASK; in brcm_stingray_scr_init() local
501 mmio_clrsetbits_32(scr_base + 0x0, clr_mask, set_mask); in brcm_stingray_scr_init()
506 mmio_clrsetbits_32(scr_base + 0x4, clr_mask, set_mask); in brcm_stingray_scr_init()
511 mmio_clrsetbits_32(scr_base + 0x8, clr_mask, set_mask); in brcm_stingray_scr_init()
516 mmio_clrsetbits_32(scr_base + 0xc, clr_mask, set_mask); in brcm_stingray_scr_init()
521 mmio_clrsetbits_32(scr_base + 0x10, clr_mask, set_mask); in brcm_stingray_scr_init()
526 mmio_clrbits_32(scr_base + 0x14, clr_mask); in brcm_stingray_scr_init()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/mcdi/ |
| A D | mt_cpu_pm_cpc.c | 77 uint32_t clr_mask = GENMASK(1, 0); in mtk_cpc_cluster_cnt_backup() local
91 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask); in mtk_cpc_cluster_cnt_backup()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/mcdi/ |
| A D | mt_cpu_pm_cpc.c | 77 uint32_t clr_mask = GENMASK(1, 0); in mtk_cpc_cluster_cnt_backup() local
91 mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask); in mtk_cpc_cluster_cnt_backup()
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