/tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/ |
A D | scp_cmd.c | 25 uint32_t code; in scp_read_response() local 27 code = mmio_read_32(CRMU_MAIL_BOX0); in scp_read_response() 28 resp->completed = code & MCU_IPC_CMD_DONE_MASK; in scp_read_response() 29 resp->cmd = code & SCP_CMD_MASK; in scp_read_response() 30 resp->ret = (code & MCU_IPC_CMD_REPLY_MASK) >> MCU_IPC_CMD_REPLY_SHIFT; in scp_read_response()
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/tf-a-ffa_el3_spmc/lib/zlib/ |
A D | inflate.h | 109 code const FAR *lencode; /* starting table for length/literal codes */ 110 code const FAR *distcode; /* starting table for distance codes */ 118 code FAR *next; /* next available space in codes[] */ 121 code codes[ENOUGH]; /* space for code tables */
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A D | inffixed.h | 10 static const code lenfix[512] = { 87 static const code distfix[32] = {
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A D | inftrees.h | 28 } code; typedef 61 unsigned codes, code FAR * FAR *table,
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/tf-a-ffa_el3_spmc/plat/brcm/board/common/ |
A D | brcm_mbedtls.c | 9 void tls_exit(int code) in tls_exit() argument 11 INFO("%s: 0x%x\n", __func__, code); in tls_exit()
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/tf-a-ffa_el3_spmc/docs/process/ |
A D | code-review-guidelines.rst | 4 This document provides TF-A specific details about the project's code review 9 Why do we do code reviews? 12 The main goal of code reviews is to improve the code quality. By reviewing each 13 other's code, we can help catch issues that were missed by the author 19 community. People with more expertise in one area of the code base can 62 - If one code owner has become unresponsive, ask the other code owners for 90 Guidelines for code owners 100 - The structure of the code is clear. 116 - (Only applicable to generic code) The code is MISRA-compliant (see 169 name clashes with generic code. [all …]
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A D | coding-style.rst | 91 .. code:: c 138 .. code:: c 150 .. code:: c 174 .. code:: c 182 .. code:: c 196 .. code:: c 213 .. code:: c 227 .. code:: c 245 .. code:: c 255 .. code:: c [all …]
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/tf-a-ffa_el3_spmc/docs/plat/ |
A D | hikey960.rst | 35 .. code:: shell 45 .. code:: shell 54 .. code:: shell 62 .. code:: shell 70 .. code:: shell 85 .. code:: shell 91 .. code:: shell 103 .. code:: shell 110 .. code:: shell 124 .. code:: shell [all …]
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A D | ti-k3.rst | 28 .. code:: shell 34 .. code:: shell 40 .. code:: shell 47 .. code:: shell 55 .. code:: shell
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A D | hikey.rst | 38 .. code:: shell 49 .. code:: shell 59 .. code:: shell 67 .. code:: shell 74 .. code:: shell 87 .. code:: shell 93 .. code:: shell 100 .. code:: shell 106 .. code:: shell 113 .. code:: shell [all …]
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A D | stm32mp1.rst | 6 It is an Armv7-A platform, using dedicated code from TF-A. 30 The STM32MP1 resets in the ROM code of the Cortex-A7. 33 The ROM code boot sequence loads the TF-A binary image from boot device 37 for ROM code is able to load this image. 87 ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot) 91 ROM code -> BL2 (compiled with BL2_AT_EL3) -> OP-TEE -> BL33 (U-Boot) 107 .. code:: bash 117 .. code:: bash
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A D | synquacer.rst | 40 .. code:: shell 48 .. code:: shell 53 - Run the following commands to clone the source code: 55 .. code:: shell 65 .. code:: shell 77 .. code:: shell 107 .. code:: shell
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A D | nvidia-tegra.rst | 9 executing both 64-bit AArch64 code, and 32-bit AArch32 code. The Carmel 24 support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code 49 (ILP) inherent in the code, Denver extracts the ILP once via software 62 support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code 71 - plat/nvidia/tegra/common - Common code for all Tegra SoCs 72 - plat/nvidia/tegra/soc/txxx - Chip specific code 84 This allows other Trusted OS vendors to use the upstream code and include 106 .. code:: shell 115 The Tegra platform code expects a pointer to the following platform specific
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A D | qemu.rst | 32 .. code:: shell 51 .. code:: shell 77 .. code:: shell 83 .. code:: shell 106 .. code:: shell 114 .. code:: shell 125 .. code:: shell 132 .. code:: shell
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/tf-a-ffa_el3_spmc/plat/rpi/rpi3/ |
A D | rpi_mbox_board.c | 31 req->code = RPI3_MBOX_PROCESS_REQUEST; in rpi3_vc_hardware_get_board_revision() 42 if (req->code != RPI3_MBOX_REQUEST_SUCCESSFUL) { in rpi3_vc_hardware_get_board_revision() 43 ERROR("rpi3: mbox: Code = 0x%08x\n", req->code); in rpi3_vc_hardware_get_board_revision()
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/tf-a-ffa_el3_spmc/docs/security_advisories/ |
A D | security-advisory-tfv-4.rst | 17 | Affected | firmware update code executing before BL31 | 34 The macro code is at line 52, referring to the version of the code as of `commit 37 .. code:: c 52 #678`_ was merged (on 18 August 2016). However, the upstream code was not 55 then, the ``check_uptr_overflow()`` macro was not used in AArch32 code. 57 The vulnerability resides in the BL1 FWU SMC handling code and it may be 60 - Platform code uses TF BL1 with the ``TRUSTED_BOARD_BOOT`` build option. 62 - Platform code uses the Firmware Update (FWU) code provided in 75 .. code:: c 97 .. code:: c [all …]
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A D | security-advisory-tfv-1.rst | 16 | Affected | firmware update code executing before BL31 | 19 | | reported by BL1 platform code | 35 The BL1 FWU SMC handling code, currently only supported on AArch64, contains 39 1. Platform code uses TF BL1 with the ``TRUSTED_BOARD_BOOT`` build option 42 2. Platform code arranges for untrusted normal world FWU code to be executed in 43 the cold boot path, before BL31 starts. Untrusted in this sense means code 47 3. Platform code copies the insecure pattern described below from the ARM 60 of the code: 64 .. code:: c 102 .. code:: c [all …]
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/tf-a-ffa_el3_spmc/plat/allwinner/sun50i_a64/ |
A D | sunxi_power.c | 226 uint32_t *code = arisc_core_off; in sunxi_cpu_power_off_self() local 238 code[0] = (code[0] & ~0xffff) | BIT_32(core); in sunxi_cpu_power_off_self() 239 clean_dcache_range((uintptr_t)code, sizeof(arisc_core_off)); in sunxi_cpu_power_off_self() 246 mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4); in sunxi_cpu_power_off_self()
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/tf-a-ffa_el3_spmc/docs/ |
A D | license.rst | 15 - Redistributions of source code must retain the above copyright notice, this 53 This project contains code from other projects as listed below. The original 56 - The libc source code is derived from `FreeBSD`_ and `SCC`_. FreeBSD uses 57 various BSD licenses, including BSD-3-Clause and BSD-2-Clause. The SCC code 60 - The libfdt source code is disjunctively dual licensed 62 the BSD-2-Clause license. Any contributions to this code must be made under 65 - The LLVM compiler-rt source code is disjunctively dual licensed 69 contributions to this code must be made under the terms of both licenses. 71 - The zlib source code is licensed under the Zlib license, which is a 74 - Some STMicroelectronics platform source code is disjunctively dual licensed [all …]
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/tf-a-ffa_el3_spmc/docs/getting_started/ |
A D | tools-build.rst | 21 .. code:: shell 27 .. code:: shell 43 .. code:: shell 49 .. code:: shell 64 .. code:: shell 73 .. code:: shell 79 .. code:: shell 88 .. code:: shell 95 .. code:: shell 118 .. code:: shell [all …]
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A D | initial-build.rst | 9 .. code:: shell 15 .. code:: shell 34 .. code:: shell 45 .. code:: shell 54 .. code:: shell 60 .. code:: shell 104 .. code:: shell 112 .. code:: shell
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/tf-a-ffa_el3_spmc/docs/plat/arm/fvp-ve/ |
A D | index.rst | 34 .. code:: shell 40 .. code:: shell 46 .. code:: shell 55 .. code:: shell 63 .. code:: shell 75 .. code:: shell
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/tf-a-ffa_el3_spmc/docs/design/ |
A D | reset-design.rst | 6 integrator can tailor this code to the system configuration to some extent, 10 document which provides greater implementation details around the reset code, 13 General reset code flow 16 The TF-A reset code is implemented in BL1 by default. The following high-level 19 |Default reset code flow| 45 |Reset code flow with programmable reset address| 58 Therefore, the cold boot code has to arbitrate access to hardware resources 67 |Reset code flow with single CPU released out of reset| 108 images might be done by the Trusted Boot Firmware or by platform code in BL31. 131 In this configuration, BL31 uses the same reset framework and code as the one [all …]
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/tf-a-ffa_el3_spmc/docs/resources/diagrams/plantuml/ |
A D | fconf_bl2_populate.puml | 3 box "BL2 common code" 8 box "platform common code" 14 box "arm platform code" #LightBlue
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/tf-a-ffa_el3_spmc/docs/plat/arm/arm_fpga/ |
A D | index.rst | 8 Some interconnect setup is done internally by the platform, so the TF-A code 33 churn. With this option, the code will fall back to some basic CPU support 34 code (only architectural system registers, and no errata). 46 The DT gets amended by the code, to potentially add a command line and 66 .. code:: shell 74 .. code:: shell 81 After building TF-A, the actual TF-A code will be located in ``bl31.bin`` in 84 as some simple ROM trampoline code (required by the Arm FPGA boot flow) and 91 .. code:: shell
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