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Searched refs:coherent (Results 1 – 11 of 11) sorted by relevance

/tf-a-ffa_el3_spmc/fdts/
A Dn1sdp.dtsi140 dma-coherent;
152 dma-coherent;
163 dma-coherent;
186 dma-coherent;
A Dn1sdp-multi-chip.dts66 dma-coherent;
77 dma-coherent;
/tf-a-ffa_el3_spmc/plat/nvidia/tegra/scat/
A Dbl31.scat242 * The base address of the coherent memory section must be page-aligned (4K)
243 * to guarantee that the coherent data are stored on their own pages and
245 * memory attributes for the coherent data page tables.
250 * Bakery locks are stored in coherent memory
/tf-a-ffa_el3_spmc/plat/imx/common/include/sci/svc/rm/
A Dsci_rm_api.h151 sc_bool_t grant, sc_bool_t coherent);
/tf-a-ffa_el3_spmc/docs/plat/
A Dnvidia-tegra.rst7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
/tf-a-ffa_el3_spmc/plat/imx/common/sci/svc/rm/
A Drm_rpc_clnt.c33 sc_bool_t grant, sc_bool_t coherent) in sc_rm_partition_alloc() argument
45 RPC_U8(&msg, 4U) = (uint8_t)coherent; in sc_rm_partition_alloc()
/tf-a-ffa_el3_spmc/docs/design/
A Dfirmware-design.rst1593 - The coherent memory section (if enabled) must be zero-initialised as well.
2009 Use of coherent memory in TF-A
2020 is the smallest possible size of the coherent memory region.
2023 mismatched attributes from various CPUs are allocated in a coherent memory
2024 region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
2036 Disabling the use of coherent memory in TF-A
2039 It might be desirable to avoid the cost of allocating coherent memory on
2040 platforms which are memory constrained. TF-A enables inclusion of coherent
2088 them from coherent memory involves only doing a clean and invalidate of the
2209 Non Functional Impact of removing coherent memory
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/tf-a-ffa_el3_spmc/docs/plat/marvell/armada/
A Dbuild.rst86 This flag determines whether to include the coherent memory region in the
/tf-a-ffa_el3_spmc/docs/
A Dchange-log.rst1628 - ti: k3: drivers: ti_sci: Put sequence number in coherent memory and
1908 - ti/k3: common: Add support for J721E, Use coherent memory for shared data, Trap all
3784 - The bakery lock structure for coherent memory has been optimised.
3949 memory as coherent. The build flag ``USE_COHERENT_MEM`` can be used to
3954 coherent memory has been added.
3956 - Memory which was previously marked as coherent is now kept coherent
4111 - Removed coherent stacks from the codebase. Stacks allocated in normal
4277 - Updated BL1 and BL2 to use a single coherent stack each, rather than one
/tf-a-ffa_el3_spmc/docs/getting_started/
A Dbuild-options.rst585 sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
674 - ``USE_COHERENT_MEM``: This flag determines whether to include the coherent
A Dporting-guide.rst68 page boundary (4K) for each BL stage. All sections which allocate coherent
506 the platform decides not to use the coherent memory section by undefining the

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